DRAM 1968 Classify Release Large Scale Memory Architecture

# Classify and Release: The Architecture That Makes Large-Scale Memory Possible

## 1. Classify the Finished Device by What It Stores and What It Requires

The completed one-transistor, one-capacitor cell is dynamic random-access memory: dynamic because charge must be restored periodically, random-access because row and column selection can address locations without stepping through all earlier locations, semiconductor because the switch, capacitor, interconnect, and peripheral circuits are integrated in a fabricated electronic structure, and volatile because loss of operating power does not preserve the stored charge indefinitely. Each part of that classification follows from behavior established in this series rather than from a name applied afterward.

The cell stores a bit as capacitor charge, grants access through a word-line-controlled MOS transistor, shares that charge with a bit line during readout, relies on sensing and write-back after the destructive read, and requires refresh before leakage removes the usable margin. It is not a static latch and it is not nonvolatile storage. Its identity is the complete set of those properties.

$$\text{DRAM cell}=\text{1 access transistor}+\text{1 storage capacitor}+\text{shared sense/restore/refresh}$$
Classification Follows Directly from the Cell's Physical Behavior each word in DRAM describes an observed architectural property 1T1C CELL charge on C_s selected by one FET BEHAVIOR addressed by row + column charge leaks with time read disturbs charge sense + restore required power loss loses state D R A M DynamicRandom Access SemiconductorVolatile Memory classification is a compact statement of storage mechanism, access method, and obligations remove refresh, restoration, or power and the architecture no longer preserves its promised state

## 2. Release the Architecture Only with Cell, Array, and Operating Evidence Together

A releasable DRAM architecture needs more than a working isolated cell. The cell must write both states, retain adequate margin across the qualified population and conditions, produce a resolvable charge-sharing signal, survive repeated access, and restore correctly. The array must select one row without disturbing others, sense columns reliably, complete refresh within the allowed window, and preserve useful bandwidth after maintenance traffic. The manufactured macro must meet density, timing, energy, and yield targets simultaneously.

Release Evidence Expands from One Cell to the Complete Memory each larger level inherits every requirement below it CELL EVIDENCE write both statesretention margincharge-sharing signal restore correctlyleakage distributionaccess endurance ARRAY EVIDENCE row isolationcolumn sensingrefresh completion read/write timingdisturb coverageusable bandwidth MACRO RELEASE qualified P/V/T envelopedensity after peripherytiming + energy limits yield and test coveragedocumented refresh ruletraceable pass criteria RELEASED: dynamic, volatile, random-access memory within its qualified envelope a passing cell is necessary; a passing array and manufactured macro make it usable

Release is therefore conditional, not ceremonial. The refresh interval belongs to an explicit process-voltage-temperature envelope and population criterion. Density is reported after peripheral area. Timing includes precharge, sensing, restoration, and maintenance. Any implementation outside those measured bounds requires new qualification rather than inheriting the label automatically.

## 3. Large-Scale Memory Becomes Possible Because Simplicity Repeats and Complexity Is Shared

The central achievement of Dennard's architecture is an asymmetry of replication. The smallest possible storage mechanism—one selectable charge reservoir—is repeated for every bit. The expensive functions that interpret, restore, and preserve those bits are placed at row and column boundaries where many cells can share them. As capacity grows, the compact cell repeats directly, while substantial portions of the control machinery are amortized across the array.

That is the through-line of this ten-step series. Step 1 separated memory from combinational logic by dependence on prior state. Step 2 moved the bit from a transistor latch into capacitor charge. Steps 3 and 4 built the access transistor and storage capacitor from process pieces already established. Steps 5 through 7 confronted leakage, refresh, and destructive readout. Steps 8 and 9 measured the density advantage and qualified its system cost. This final step classifies the result: a compact dynamic cell whose local incompleteness is precisely what allows shared machinery to support large arrays.

The released architecture is not valuable because the capacitor remembers perfectly—it does not. It is valuable because one transistor and one capacitor remember long enough for shared circuitry to maintain them, allowing far more bits to occupy a substrate than a locally regenerated latch architecture could provide under comparable process rules. That redistribution of complexity is what makes large-scale semiconductor memory possible.

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