3D DRAM Staircase Etch

The 3D-DRAM staircase etch terraces down through the same Si/SiGe superlattice this project's two previous rounds already cut and selectively hollowed out, repeating a trim-and-etch cycle at the stack's edge to expose each individual layer's own buried bitline at a different horizontal position — a genuinely different problem from this site's 3D NAND staircase etch, which terraces through a much taller oxide-nitride stack to land word-line contacts rather than bitline contacts, and does so across 200 to 300-plus layers rather than the far shorter stack a 4F² vertical-channel array actually needs. A single etch step produces one depth everywhere it runs, but every layer in this stack has its own buried bitline trench, covered a few rounds earlier in this project, that needs an independent electrical landing point from above; the staircase etch solves that by narrowing the resist mask one increment at a time between etch cycles, so each cycle clears one more layer while the layers already exposed keep stepping down and outward into a receding terrace shape.

Far fewer layers than 3D NAND's staircase changes the engineering tradeoffs considerably, even though the repeated trim-etch mechanism is identical in principle. A 3D NAND staircase spends more process time than almost any other single etch module in that flow precisely because 200 to 300-plus word lines each demand their own trim-etch cycle; a 4F² vertical-channel array's staircase, terracing through a stack with far fewer Si/SiGe layer pairs, runs far fewer cycles for the same reason the underlying architectures differ — a DRAM cell's bitline count per vertical stack is nowhere near NAND's layer count, so this staircase etch's total cycle time and cumulative depth-control burden scale down accordingly, even while it borrows the exact same trim-and-etch loop mechanism this site's NAND staircase etch article covers in detail.

Landing on a buried bitline rather than a word line changes what "successfully exposing a layer" actually means at the bottom of each step. The NAND staircase's goal is exposing each conductive word-line layer in a charge-storage stack for a contact that will eventually control that layer's access transistors; this staircase instead has to expose the buried bitline trench this project covered earlier, which is the horizontal data path rather than a cell-select signal, so the depth-check metrology running inside each trim-etch cycle here is confirming contact to a completely different electrical function than the equivalent check in the NAND flow, even though both checks exist for the identical structural reason — verifying the terrace actually stopped at the right layer before moving to the next trim.

Read through a shared-mechanism-different-destination lens, the 3D-DRAM staircase etch closes this project's entire original roadmap the same way it opened Section 11 — by taking a technique this site has already documented in full detail for a different architecture and showing that the underlying trim-and-etch idea travels, while the number of layers, the electrical target at the bottom of each step, and the surrounding cell architecture are specific enough to this emerging 4F² design that none of it can simply be copied over wholesale from what NAND or production horizontal-cell DRAM already does.