dual-stress liner

**Dual-Stress Liner (DSL)** is a **process integration technique that applies different stress types to NMOS and PMOS transistors on the same die** — depositing tensile SiN over NMOS regions and compressive SiN over PMOS regions using selective deposition and etch. **How Does DSL Work?** - **Process**: 1. Deposit compressive SiN blanket over entire wafer. 2. Mask and etch away compressive SiN from NMOS regions. 3. Deposit tensile SiN blanket. 4. Mask and etch away tensile SiN from PMOS regions. - **Result**: Each transistor type has its optimal stress liner. **Why It Matters** - **Simultaneous Boost**: Both NMOS and PMOS benefit (~15-25% each), unlike single-stress liner which helps one at the expense of the other. - **Industry Standard**: Used from 65nm through 28nm by all major foundries. - **Cost**: Requires extra lithography and etch steps (2 additional masks). **Dual-Stress Liner** is **custom tailoring stress for each transistor type** — giving NMOS and PMOS each their own performance-boosting strain on the same chip.