embedded SiGe

**Embedded SiGe Source/Drain** is **a strain engineering technique that selectively grows epitaxial silicon-germanium (SiGe) in recessed source/drain cavities adjacent to the PMOS channel, introducing uniaxial compressive stress along the channel direction to enhance hole mobility and boost PMOS drive current** — first introduced at the 90 nm node and remaining an indispensable performance enhancement through FinFET and nanosheet architectures. - **Process Flow**: After gate patterning and spacer formation, the silicon in the PMOS source/drain regions is selectively etched to create sigma-shaped or U-shaped cavities using anisotropic dry etch followed by wet etch in tetramethylammonium hydroxide (TMAH) that exposes specific crystallographic facets; epitaxial SiGe is then grown by chemical vapor deposition (CVD) using dichlorosilane (DCS) and germane (GeH4) precursors with HCl for selectivity. - **Germanium Content**: Higher germanium concentration generates greater lattice mismatch with the silicon channel, producing stronger compressive stress; germanium fractions have increased from 20-25 percent at the 90 nm node to 35-45 percent at the 14 nm node, with some processes incorporating graded compositions to manage strain relaxation. - **Sigma-Shaped Recess**: The TMAH etch creates a faceted cavity bounded by slow-etching (111) planes that extends beneath the spacer edge, bringing the SiGe stressor closer to the channel and maximizing the compressive stress at the carrier inversion layer; the tip-to-channel proximity is a critical parameter that determines the magnitude of mobility enhancement. - **Selective Epitaxy**: Growth selectivity between silicon and dielectric surfaces is maintained by balancing deposition and etch rates through HCl flow optimization; loss of selectivity causes polycrystalline SiGe nodules on oxide and nitride surfaces that can create shorts or increase leakage at subsequent process steps. - **In-Situ Boron Doping**: The source/drain SiGe is heavily doped with boron during epitaxial growth (concentrations of 2-5e20 per cubic centimeter) to simultaneously form low-resistance raised source/drain regions and abrupt junctions; in-situ doping eliminates the need for high-energy implantation that could damage the epitaxial crystal quality. - **Faceting Control**: Epitaxial growth rates vary with crystal orientation, producing faceted surfaces that affect subsequent silicide uniformity and contact resistance; process conditions are tuned to minimize (111) facet exposure at the top surface while maintaining the desired profile shape. - **Strain Relaxation Management**: Exceeding the critical thickness for a given germanium fraction risks misfit dislocation formation that partially relaxes the strain and degrades device reliability; multi-step graded compositions and optimized growth temperatures mitigate relaxation. Embedded SiGe remains one of the most effective single-knob performance enhancers in CMOS technology, and its principles have extended to embedded SiC for NMOS tensile stress and to high-germanium SiGe channels in future device architectures.