gate-first vs gate-last

**Gate-First vs. Gate-Last** is the **fundamental choice in high-k metal gate (HKMG) integration** — whether the high-k dielectric and metal gate are formed before (gate-first) or after (gate-last/replacement metal gate) the source/drain high-temperature activation anneal. **Gate-First Approach** - **Sequence**: Deposit high-k + metal gate → pattern gate → implant S/D → high-temperature anneal. - **Advantage**: Simpler process flow, fewer steps. - **Challenge**: Metal gate must survive >1000°C S/D anneal — limits metal choices and causes V$_t$ instability. **Gate-Last (RMG) Approach** - **Sequence**: Use dummy poly gate → complete S/D → remove dummy gate → deposit high-k + metal gate. - **Advantage**: Metal gate is never exposed to high temperatures — better V$_t$ control and more metal options. - **Challenge**: Complex process flow (CMP to expose dummy gate, selective removal, metal fill). **Why It Matters**: Gate-last (RMG) has become the industry standard from 28nm onward due to superior threshold voltage control and work function tuning.