Intel-18a-P
Intel 18A-P is the performance-enhanced version of Intel's 18A process — the same RibbonFET gate-all-around transistors and PowerVia backside power delivery as 18A, tuned for more performance per watt and positioned as design-compatible so that customers can move from 18A without starting over. It matters because it is Intel Foundry's first refinement of its comeback node, and the clearest test of whether Intel can run a process family the way the rest of the foundry industry does: ship a base node, learn from it, then harvest gains on the same rules. At a high level, how 18A-P builds on the 18A base looks like this:
A few things are worth knowing about why 18A-P is a refinement and why it matters for Intel's foundry business and for AI and client silicon:
The base node already carries the big architectural bets. Intel 18A combines two changes at once: RibbonFET, its gate-all-around transistor in which the gate wraps stacked nanosheets, and PowerVia, which moves the power network to the back of the wafer so the front is free for signal wiring. Together they target better electrostatic control, lower IR drop, and less routing congestion. 18A-P does not replace either; it keeps both and tunes the process around them.
The headline gain is modest and deliberately compatible. Intel states that 18A-P offers up to roughly 9% better performance per watt than 18A, and positions it as a design-compatible enhancement rather than a new set of rules. As with other refinement nodes in the industry, the point is not a generational leap: it is that a design already working on the base process can capture extra speed or efficiency with limited rework, on a line whose defect and variability data are already maturing.
Three kinds of tuning add up. First, the transistor and contact stack: because current must pass through source and drain, contacts, and local wiring, series resistance can rival the channel itself at these dimensions, so lowering it lifts drive current. Second, the backside connection and its thermal path: with power wiring on the back, heat has a different route out of the die, so the contact and thermal design matter. Third, signal-wire resistance and the standard-cell library, which affect every switching path.
The family continues with 18A-PT. Intel has described 18A-PT as an extension aimed at 3D-stacked designs, using fine-pitch hybrid bonding, reportedly in the low single-digit micrometer range, to join dies vertically. That targets chiplet-heavy AI and server products, where bandwidth between dies and power delivery to stacked logic are the limiting factors. 18A-P is the general performance variant; 18A-PT is the packaging-oriented one.
Why the refinement matters strategically. For a foundry trying to win outside customers, a base node proves the technology but a compatible refinement proves the roadmap: it shows customers that investing in 18A design rules will pay off again without a rewrite. That is the same logic that made enhanced nodes valuable elsewhere in the industry, applied to a new transistor and a new power-delivery scheme at the same time.
The risks are real. Backside power and gate-all-around together raise process complexity, and a refinement must preserve yield while changing recipes. Customers will judge 18A-P by delivered yield, schedule, and measured performance per watt on real products, not by its headline ratio.
Read 18A-P through a *compatibility-times-gain* lens rather than a *node-name* lens: the number that decides whether it is the right choice is how much extra performance per watt a design recovers per unit of migration risk on a RibbonFET and PowerVia base — and 18A-P is the node built to show that Intel's new architecture can be improved in place.