Intel-18a-Pt

Intel 18A-PT is an Intel 18A-family technology designed to serve as an active base die in advanced three-dimensional integrated circuits. It combines the family’s RibbonFET gate-all-around devices and backside-power approach with interfaces and vertical connections for stacked chiplets. Its significance is the meeting of transistor technology and packaging: the base can contain useful logic while connecting a compute tier above it to the rest of the system.

Partition the system
Top compute tier
Process and die boundary
Active base tier
Logic and vertical routes
Co-design the stack
Signals and power
Hybrid bonds, TSVs, backside
Thermal and test
Heat paths and test access
Build a qualified system
Bond and assemble
Foveros Direct 3D integration
Package sign-off
Yield, timing and lifetime

The base die is an active part of the computer. A passive interposer primarily supplies interconnects; an active base includes transistors and can implement functions chosen by the system designer. Intel describes 18A-PT as a base-die technology with backside power delivery and advanced 3D integration features. It does not prescribe one universal cache, I/O or control architecture. The partition must decide what belongs in the base, what belongs in each top die and how much traffic crosses their boundaries.

Foveros Direct connects the facing surfaces. Intel’s April 2025 disclosure describes connecting 18A-PT to a top die using Foveros Direct 3D, with a hybrid-bonding interconnect pitch below 5 micrometers. Hybrid bonding joins dielectric surfaces and copper contacts at the interface, rather than placing a conventional solder ball at every fine-pitch connection. The figure is a dated vendor disclosure for that integration approach; it is not an instruction to assign the same pitch to every Foveros generation or every manufactured product.

Intel 18A-PT: The Active Base of a 3D System Dense signals above the base die · backside power below it Top compute chiplet top-die devices Foveros Direct 3D Cu-to-Cu hybrid bonding Frontside BEOL Dense signal interconnects thinned base silicon package-side connections Compute tier Process chosen per design Active base die RibbonFET nanosheet logic Backside power PowerVia feeds the devices Pass-through TSVs Illustrative vertical I/O routes Distinct from nano-PowerVias Conceptual topology only: die thicknesses, sheet count and via dimensions are not to scale.

Backside power and frontside signals have different jobs. PowerVia brings supply current toward the devices from the backside, while frontside metal remains available for dense signal routing and connections to the upper tier. This can reduce competition for routing resources, but useful results still depend on the power grid, local current demand, capacitance and voltage droop. RibbonFET describes the transistor architecture; PowerVia describes a power-delivery integration; Foveros Direct describes die-to-die bonding. They operate at different physical levels of the system.

The vertical connections are not interchangeable. Intel lists pass-through TSVs, die-to-die TSVs and a hybrid bonding interface among 18A-PT’s integration capabilities. A through-silicon via traverses silicon to provide a vertical electrical path; the hybrid interface joins two die surfaces. The much smaller device-power connections associated with PowerVia solve another problem. The simplified drawing uses separate colors and intentional clearances so that an illustrative I/O route is not mistaken for a connection to the backside supply plane.

Three Vertical Connections, Three Different Jobs A hybrid bond is not a solder bump, and a pass-through TSV is not a nano-PowerVia Hybrid interface die surface ↔ die surface Pass-through TSV vertical route through silicon PowerVia backside supply → device Connection dimensions are intentionally not drawn to a shared scale.

Thermal paths and test access must be designed before bonding. Closely stacked logic can improve communication density while making heat removal and failure isolation harder. Designers need a realistic power map, a heat path through the assembled stack, test access to each tier and a way to assess bonding quality. Screening known-good dies reduces risk, but it does not eliminate interface defects or failures that appear only after assembly. The economically useful output is a qualified working stack, rather than two individually good dies.

18A-family production does not establish every derivative’s readiness. Intel’s current process page identifies the base Intel 18A platform as being in high-volume production and describes 18A-PT separately. Its 2025 announcement positions PT as building on the performance and power advances of 18A-P. Neither statement alone establishes broad volume shipment of a particular 18A-PT stack. For a product decision, the relevant evidence is the exact PDK, supported bonding flow, partner enablement, reliability qualification and customer-production milestone for that implementation.

Sources and further reading. [Intel 18A-family technology description](https://www.intel.com/content/www/us/en/foundry/process/18a.html); [Intel Foundry Direct Connect disclosure, April 29, 2025](https://www.intel.com/content/www/us/en/newsroom/news/corporate/intel-foundry-gathers-customers-partners-outlines-priorities.html).

Read Intel 18A-PT as an active foundation for a stacked system: judge its devices, bonding interface, vertical routes, power delivery, thermal design and test strategy as one integrated architecture.

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