latchup testing

**Latchup Testing** is a **reliability test that verifies an IC's immunity to latchup** — a condition where a parasitic thyristor (PNPN structure) in CMOS turns on, creating a low-resistance path from VDD to GND that can destroy the device. **What Is Latchup Testing?** - **Trigger Methods**: - **I-Test**: Inject current into I/O pins (±100 mA typical) to forward-bias parasitic junctions. - **V-Test**: Apply overvoltage/undervoltage to pins (above VDD or below GND). - **Supply Overvoltage**: Ramp VDD above maximum rating. - **Pass Criteria**: Supply current ($I_{DD}$) must not increase by more than a specified amount. - **Standard**: JEDEC JESD78. **Why It Matters** - **Destructive**: Once triggered, latchup can draw amps of current, causing thermal destruction in milliseconds. - **Automotive Mandate**: AEC-Q100 requires latchup testing at 125°C (worst case — latchup susceptibility increases with temperature). - **Design Rules**: Adequate guard rings, well ties, and substrate contacts are the primary defenses. **Latchup Testing** is **the trip-wire test for parasitic thyristors** — ensuring that no combination of electrical stress can trigger the self-destructive feedback loop hidden in every CMOS chip.