metal gate work function

**Metal Gate Work Function and Threshold Voltage Tuning** is the **engineering of multi-layer metal gate stacks — combining different metallic thin films, interface dipoles, and doping techniques — to precisely set transistor threshold voltage (Vt) across multiple values (typically 3-5 Vt flavors) for both NMOS and PMOS devices on the same chip**. Multi-Vt design enables power-performance optimization: low-Vt transistors for speed-critical paths and high-Vt transistors for leakage-sensitive paths. The threshold voltage of a MOSFET is determined by: Vt = Φms + 2ΦF + Qox/Cox + Qdep/Cox, where Φms is the metal-semiconductor work function difference, ΦF is the Fermi potential, Qox is oxide charge, and Qdep is depletion charge. In the high-k/metal gate (HKMG) era, Φms — controlled by the gate metal work function — is the primary Vt tuning knob. NMOS requires an effective work function (EWF) near ~4.1-4.3 eV (conduction band edge), while PMOS requires ~4.8-5.0 eV (valence band edge). Work function metal (WFM) stacks typically include: **TiN** — baseline metal with EWF ~4.6-4.7 eV (midgap), used as a starting point and adhesion layer. **TiAl or TiAlC** — aluminum incorporation reduces EWF toward ~4.1 eV for NMOS tuning. The TiAl layer thickness (0.5-2nm) modulates the EWF shift. **TaN** — provides higher EWF (~4.8 eV) and serves as a barrier and PMOS WFM component. The layer stack order, individual layer thicknesses, and deposition conditions (temperature, plasma vs. thermal ALD) all affect the final EWF. For **multi-Vt implementation**, the integration flow typically uses selective removal of WFM layers by lithography and wet etch within the replacement metal gate trench: the standard Vt (SVT) stack uses the full WFM stack; low Vt (LVT) removes one TiN layer; ultra-low Vt (uLVT) removes additional layers; and high Vt (HVT) adds extra TiN layers. Each Vt flavor requires its own litho/etch sequence, making multi-Vt one of the most complex patterning challenges in the entire process flow. **Interface dipole engineering** is an additional Vt tuning mechanism: inserting thin (~0.3-0.5nm) dielectric dipole layers (La2O3 for NMOS Vt reduction, Al2O3 for PMOS Vt reduction) at the interfacial layer/high-k interface creates a fixed charge dipole that shifts the effective work function without changing the metal stack. This technique provides Vt shifts of 50-200mV and is increasingly important as the physical space for WFM layers shrinks in GAA/nanosheet architectures where the inter-sheet gap may be only 8-10nm. At **nanosheet/GAA nodes**, Vt tuning faces acute challenges: the WFM stack must fit within the narrow gap between nanosheet channels while providing distinct work functions for multiple Vt flavors. This drives extreme thinning of individual WFM layers (sub-1nm) and increased reliance on dipole engineering rather than metal thickness modulation. **Metal gate work function engineering is the most dimensionally constrained optimization problem in advanced CMOS — fitting multiple metallic layers with angstrom-level precision into sub-10nm spaces while hitting Vt targets within ±10mV tolerance across billions of transistors.**