Microprocessor 1971 Step 15 Specs Deep Dive Transistor Count Process Node Clock

# Put Numbers on the Chip: Transistor Count, Process Node, and Clock Rate Behind Steps 1 Through 10

## 1. The Figures Earlier Steps Used Qualitatively, Stated Exactly

Steps 1 through 10 of this series describe the 4004's structure — decoder, arithmetic unit, registers, bus multiplexing — without stating the physical numbers those structures were actually built at, because the architecture, not the manufacturing figures, was each step's subject. Those numbers are not a footnote; they explain why the 4004's architecture had to be as compact as Step 2's word-width compromise and Step 8's instruction-cycle accounting describe.

The 4004 was fabricated using a 10-micrometer silicon-gate PMOS process and contained approximately 2,300 transistors on a die roughly 3 millimeters by 4 millimeters. It ran its instruction cycle, built from the two-phase and later multi-phase clocking Step 7 describes, at a clock rate of 740 kilohertz, executing a basic machine cycle in several clock periods rather than one — the discrete-logic comparison in Step 8 is measured against that clock rate, not against a faster figure sometimes quoted for later microprocessors in the same family.

The 4004's Physical Numbers, Stated Once and Precisely what Steps 1-10 built their architectural account on top of PROCESS 10 µm silicon-gate PMOS the feature size Steps 4/12 assume as given TRANSISTOR COUNT ~2,300 on a ~3mm x 4mm die the transistor budget Step 2's word choice fits inside CLOCK RATE 740 kHz multi-phase, per Step 7 the rate Step 8's cycle-count comparison uses THESE THREE NUMBERS CONSTRAIN EACH OTHER a 10µm process bounds how many of the 2,300 transistors fit on an affordable die; transistor count and clock rate together bound how much logic the cycle time can afford to do at once

## 2. Why the Instruction Cycle Could Not Simply Run Faster

A reasonable question Step 8's discrete-logic comparison invites but does not answer: why 740 kilohertz, rather than a higher clock rate that would have made the integration advantage even larger? The answer is in the process and transistor figures above, not in a separate design choice. PMOS transistors at a 10-micrometer feature size switch more slowly than the NMOS and later CMOS processes this project's own later series (`hmos_1978`, `cmos_logic_1980s`, named here only, not retold) eventually used, and the multiplexed bus architecture Step 3 and Step 7 describe requires multiple clock phases to complete operations a single-purpose circuit could finish in one. Raising the clock rate without changing the process or the multiplexing scheme would have outrun the PMOS circuits' own switching speed, producing errors rather than more throughput.

The 4004's clock rate is therefore not an arbitrary historical figure; it is the rate that this specific process, this specific transistor budget, and this specific multiplexed architecture could support together, each constraint already established by a different earlier step in this series.

Three Constraints Converging on One Clock Rate 740 kHz is where process speed, transistor budget, and bus multiplexing all agree PMOS switching speed10µm process limit transistor budgetStep 2's compromise multiplexed bus phasesSteps 3 and 7 740 kHz the rate all three constraints support together

## 3. What These Numbers Do and Do Not Explain

These figures sharpen, rather than revise, every earlier step's architectural account. They do not change Step 1's thesis about program-defined behavior, Step 5's arithmetic design, or Step 9's flexibility-versus-speed framing — they give those claims a concrete scale. A 2,300-transistor, 10-micrometer, 740-kilohertz chip is a specific, dateable object, not an abstract description of "a microprocessor"; stating its numbers precisely is what lets later comparisons — against the TMS 1000's own transistor count, against the 8008's wider word, against any modern processor — be made on stated figures rather than impressions.

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