nanosheet

**Nanosheet Channel Release Etch and Inner Spacer Formation** is **the critical pair of process steps in gate-all-around (GAA) nanosheet transistor fabrication where the sacrificial SiGe layers in a Si/SiGe superlattice are selectively removed to release free-standing silicon channel nanosheets, and inner spacer dielectrics are formed in the resulting cavities to isolate the gate from the source/drain regions** — together defining the electrostatic control and parasitic capacitance of the most advanced transistor architecture in production. - **Superlattice Growth**: Alternating layers of silicon (channel) and SiGe (sacrificial) are epitaxially grown on the substrate, typically 3-5 pairs with each layer 5-8 nm thick; the SiGe composition (25-35 percent germanium) is chosen to provide sufficient etch selectivity to silicon during the release step. - **Channel Release Etch**: After dummy gate removal in the replacement metal gate flow, the exposed SiGe sacrificial layers are selectively etched using vapor-phase or wet chemistries such as hydrochloric acid vapor or acetic acid/hydrogen peroxide/HF mixtures that achieve selectivity exceeding 100:1 to silicon; the etch must completely remove SiGe between the nanosheets without attacking the silicon channels or undermining the structural support at the sheet edges. - **Etch Uniformity**: Channel release must be uniform across all nanosheet layers and across the wafer; incomplete release leaves SiGe residues that degrade gate coverage and increase variability, while over-etching can thin the silicon channels or undercut into the source/drain epitaxial regions. - **Inner Spacer Recess**: Before channel release, the SiGe layers are laterally recessed from the source/drain cavity edges by a controlled amount (typically 3-7 nm) using selective isotropic etching; this recess defines the volume for inner spacer formation. - **Inner Spacer Deposition**: A conformal dielectric film (SiN, SiOCN, or SiCO with k-value of 4-6) is deposited by ALD to fill the lateral recesses; the inner spacer material must provide low gate-to-source/drain capacitance, adequate isolation voltage, and compatibility with subsequent processing temperatures. - **Inner Spacer Etch-Back**: Anisotropic etching removes the inner spacer material from all surfaces except within the lateral recesses, leaving precisely shaped dielectric plugs that separate the gate metal from the source/drain regions; the etch-back uniformity directly determines parasitic capacitance variation. - **Structural Integrity**: During channel release, the unsupported nanosheet segments must maintain their shape without bending or stiction; nanosheet width, length, and the spacing between anchor points at the source/drain are designed to prevent mechanical failure during wet processing and drying. - **Surface Preparation**: After release, the exposed silicon nanosheet surfaces are cleaned and passivated with a thin chemical oxide before high-k ALD gate dielectric deposition; surface roughness and contamination on these all-around surfaces directly impact channel mobility and threshold voltage uniformity. Nanosheet channel release and inner spacer formation are among the most challenging process steps in semiconductor manufacturing, as they require angstrom-level precision in three dimensions to achieve the electrostatic and parasitic performance that motivates the transition from FinFET to GAA architectures.