poly cmp

Poly CMP polishes polysilicon films for gate electrode planarization, replacement metal gate (RMG) processes, and polysilicon plug applications in semiconductor manufacturing. In the traditional poly gate flow, deposited polysilicon is planarized to create uniform gate height across varying topography. In the replacement metal gate process used at 28nm and below, sacrificial poly gates are polished to expose them for subsequent removal and replacement with high-k/metal gate stacks. Poly CMP uses silica-based alkaline slurries (pH 10-12) that achieve chemical-mechanical removal through oxidation of the polysilicon surface followed by abrasive removal of the oxidized layer. Removal rates are typically 1500-3000 Å/min with good selectivity to oxide (poly:oxide selectivity of 20:1 to 50:1 depending on slurry chemistry). Key challenges include achieving uniform poly thickness across the wafer (within-wafer non-uniformity < 3%), controlling dishing in wide poly features, minimizing microscratches that could damage the thin gate oxide underneath, and avoiding grain-boundary preferential etching that creates surface roughness. For FinFET processes, poly CMP planarity requirements are extremely stringent as the polished poly surface defines the gate height uniformity across billions of fins on a single die. Endpoint detection typically uses optical monitoring or motor current change when the polish reaches the underlying oxide layer.