polysilicon gate depletion
**Polysilicon Gate Depletion** is the **parasitic effect where the heavily-doped polysilicon gate electrode develops a depletion region at the poly/oxide interface under inversion bias**, effectively adding a series capacitance that reduces the total gate capacitance by 5-15% and degrades transistor drive current — historically one of the primary motivations for the industry's transition from polysilicon to high-k/metal gate (HKMG) technology.
**The Mechanism**: Polysilicon gates are doped to ~10²⁰ cm⁻³ (the solid solubility limit). Although this is extremely heavy doping, it is NOT metallic (not infinite carrier density). When the transistor is in inversion, the electric field at the gate electrode surface pushes carriers away from the poly/oxide interface, creating a thin (~0.3-0.5nm) depletion region in the polysilicon. This depletion region acts as a series capacitor with the gate oxide.
**Capacitance Impact**: The effective oxide thickness (EOT) becomes: EOT_eff = EOT_physical + t_poly_depletion. With physical EOT of ~1.0nm and poly depletion of ~0.4nm, the effective EOT is ~1.4nm — a 40% penalty. As physical oxides thinned, poly depletion became an increasingly dominant fraction of the total effective thickness, eventually consuming most of the benefit of thinner gate oxides.
**Quantitative Degradation**:
| Physical EOT | Poly Depletion | Effective EOT | Penalty |
|-------------|----------------|--------------|--------|
| 3.0nm | 0.4nm | 3.4nm | 13% |
| 2.0nm | 0.4nm | 2.4nm | 20% |
| 1.2nm | 0.4nm | 1.6nm | 33% |
| **1.0nm** | **0.4nm** | **1.4nm** | **40%** |
As EOT scaled below ~1.5nm, the poly depletion penalty became intolerable.
**Metal Gate Solution**: Metal gate electrodes have essentially infinite carrier density — no depletion region forms regardless of bias. Replacing polysilicon with metal eliminates the ~0.4nm poly depletion component entirely, recovering the lost capacitance. Combined with high-k dielectric (which replaces SiO₂ to achieve low EOT with physically thicker oxide, reducing tunneling leakage), the HKMG stack resolved both the poly depletion and gate leakage problems simultaneously.
**Gate-First vs. Gate-Last HKMG**: Two integration approaches exist: **gate-first** (deposit HKMG before S/D processing — simpler but metal must survive high-temperature anneals) and **gate-last (replacement metal gate, RMG)** (use a sacrificial poly gate through S/D processing, then replace with metal after annealing — more complex but better metal gate quality). The industry largely converged on RMG for logic at 28nm and below.
**Work Function Metal Engineering**: With poly gates, V_th was adjusted by changing channel doping. With metal gates, V_th is primarily set by the gate metal's work function. Multiple threshold voltages (SVT, RVT, LVT, ULVT) on the same chip require different metal stacks — achieved by selective deposition and removal of thin work function metal layers (TiN, TiAl, TaN), adding significant process complexity.
**Polysilicon gate depletion stands as a textbook example of how parasitic effects in scaling can drive fundamental architectural transitions — where a seemingly minor capacitance penalty accumulated to the point of requiring a complete reimagining of the gate stack, catalyzing the HKMG revolution that redefined CMOS technology.**