Samsung-Sf2
Samsung’s 2nm-class MBCFET platform. SF2 is Samsung Foundry’s 2nm-class logic technology, described in its process catalog as a second-generation MBCFET gate-all-around platform. It continues the nanosheet direction established in Samsung’s 3nm generation. The designation covers a manufacturing platform and supporting design ecosystem. It does not describe a literal two-nanometer gate or establish equivalence with another supplier’s N2 or angstrom-branded process.
A second generation involves more than renaming. A nanosheet platform can refine channel geometry, contacts, isolation, standard cells, and wiring to improve the operating tradeoffs available to designers. Because sheet width influences drive capability and capacitance, device choices and cell architecture must be optimized together. The benefits visible in an isolated device are constrained by the routed circuit, memory content, voltage, temperature, and manufacturing variation.
A reported production milestone. Samsung’s results published on January 29, 2026 state that its foundry business commenced mass production of first-generation 2nm products in the fourth quarter of 2025. This is a dated company report of production, rather than an earlier roadmap target. It does not disclose a universal yield figure or establish that every announced SF2 derivative and application-specific qualification was simultaneously available.
Variants and power delivery need explicit names. A process family may grow into performance, automotive, or other specialized releases. Backside power delivery is another integration option, not a consequence of using gate-all-around transistors. A comparison should identify the exact variant before assigning backside routing, reliability qualification, or application support to it. Foundry-level roadmap descriptions are broader than the manufacturing specification of a particular chip.
Compare customer outcomes at matched conditions. Useful evidence includes timing and power for routed blocks, SRAM operation, interface support, reliability, and production learning. A PDK and qualified IP make the technology usable in a design flow, while packaging and supply commitments determine whether the finished product can ship. The most meaningful benchmark states its baseline and workload, rather than inferring superiority from the difference between two node labels.
Sources and further reading. [Samsung logic-node catalog](https://semiconductor.samsung.com/foundry/process-technology/logic-node/); [Samsung January 2026 earnings release](https://news.samsungsemiconductor.com/global/samsung-electronics-announces-fourth-quarter-and-fy-2025-results/).
Read Samsung SF2 as a reported-production GAA platform that must be specified by variant and evaluated at circuit level.