source drain engineering

**Source/Drain Engineering** is **the comprehensive set of techniques for forming low-resistance, shallow, and abrupt source/drain junctions — including ultra-shallow extensions (USJ), raised epitaxial regions, silicide contacts, and optimized implant/anneal processes that minimize parasitic resistance while controlling short-channel effects in sub-100nm transistors**. **Source/Drain Extensions (SDE):** - **Purpose**: lightly-doped extensions under the gate edge provide gradual doping transition and reduce peak electric field at the drain junction; critical for controlling drain-induced barrier lowering (DIBL) and hot carrier degradation - **Implant Conditions**: low-energy (0.5-2keV) arsenic or phosphorus for NMOS extensions; boron or BF₂ (0.3-1keV) for PMOS; ultra-low energy minimizes channeling and produces junction depths of 10-20nm at 65nm node, scaling to 5-8nm at 22nm - **Dose Requirements**: extension dose 1-3×10¹⁴ cm⁻² provides sheet resistance 1-2kΩ/sq; higher dose reduces resistance but increases junction capacitance and short-channel effects; dose optimization balances Ron and SCE - **Offset Spacers**: thin oxide or nitride spacer (5-10nm) protects the gate during extension implant; spacer width controls extension-to-gate overlap; narrower spacers reduce series resistance but increase gate-drain capacitance **Deep Source/Drain Formation:** - **High-Dose Implants**: after sidewall spacer formation, high-dose implants (3-8×10¹⁵ cm⁻²) at moderate energy (10-30keV) form the deep source/drain regions; arsenic for NMOS (lower diffusivity than phosphorus), boron for PMOS - **Activation Anneals**: rapid thermal anneal (RTA) at 1000-1050°C for 1-5 seconds, or spike anneal (ramp to 1050-1100°C with zero soak time) activates dopants while minimizing diffusion; millisecond laser anneals provide even less diffusion for sub-22nm nodes - **Junction Depth**: deep S/D junctions 40-80nm at 65nm node, scaling to 20-40nm at 22nm; shallower junctions reduce short-channel effects but increase series resistance; junction depth typically 0.5-0.8× gate length - **Abruptness**: junction abruptness (doping gradient) affects both SCE and resistance; abrupt junctions (10nm/decade) preferred for SCE control; achieved through low-diffusivity dopants (arsenic) and minimal thermal budget **Raised Source/Drain (RSD):** - **Selective Epitaxy**: after S/D implants, selective silicon epitaxy raises the source/drain surface 20-60nm above the original silicon level; provides more volume for silicide formation and reduces contact resistance - **Growth Chemistry**: SiH₂Cl₂ or SiH₄ with HCl at 600-750°C; HCl etches nucleation on dielectric surfaces, ensuring growth only on exposed silicon; in-situ doping with PH₃ (NMOS) or B₂H₆ (PMOS) provides high active doping (>10²⁰ cm⁻³) - **Facet Control**: epitaxial growth naturally forms {111} facets; growth conditions and dopant species affect facet angles; controlled faceting ensures uniform silicide thickness and prevents gate-to-S/D shorts - **Stress Benefits**: raised SiGe source/drain for PMOS (discussed in strain engineering) combines the resistance benefits of RSD with compressive channel stress; dual benefit of performance enhancement and parasitic reduction **Silicide Formation:** - **Nickel Silicide (NiSi)**: replaced cobalt silicide at 90nm node; lower formation temperature (400-550°C vs 700-900°C for CoSi₂), lower silicon consumption (1.84:1 Si:Ni vs 3.64:1 for Co), and better morphology on narrow lines - **Salicidation Process**: deposit 5-15nm nickel, first anneal at 300-350°C forms Ni₂Si, strip unreacted Ni with H₂SO₄/H₂O₂, second anneal at 450-550°C converts to low-resistivity NiSi phase (14-20 μΩ·cm) - **Phase Control**: NiSi is stable to 750°C; higher temperatures form high-resistivity NiSi₂; platinum addition (Ni₀.₉Pt₀.₁) stabilizes NiSi phase to 800°C, enabling compatibility with higher thermal budgets - **Narrow Line Effects**: NiSi agglomeration on narrow poly gates (<50nm) causes high resistance and variability; requires careful control of Ni thickness, anneal temperature, and Pt doping to maintain continuous silicide films **Parasitic Resistance Components:** - **Series Resistance Breakdown**: total Ron = Rext + Rsd + Rcontact where Rext is extension resistance (30-40% of total), Rsd is deep S/D resistance (20-30%), Rcontact is contact/silicide resistance (30-40%) - **Scaling Challenges**: as gate length scales, intrinsic channel resistance decreases but parasitic resistance remains relatively constant; at 22nm node, parasitic resistance is 40-50% of total Ron vs 20-30% at 130nm - **Optimization Strategies**: raised S/D reduces Rsd and Rcontact; higher extension dose reduces Rext but worsens SCE; silicide thickness optimization balances resistance and silicon consumption - **Contact Resistance**: NiSi/silicon contact resistance 1-3×10⁻⁸ Ω·cm² depends on doping concentration and silicide quality; requires active doping >10²⁰ cm⁻³ at the contact interface Source/drain engineering is **the critical enabler of scaled CMOS performance — the combination of ultra-shallow junctions, raised epitaxial regions, and optimized silicide contacts reduces parasitic resistance to manageable levels while maintaining the electrostatic control necessary for sub-50nm gate length transistors**.