source drain epitaxy process
**Source/Drain Epitaxy** is the **CMOS process module that grows crystalline semiconductor material (SiGe:B for PMOS, Si:P for NMOS) in the transistor's source and drain regions using selective epitaxial growth — replacing ion implantation as the primary doping method at advanced nodes while simultaneously introducing channel strain that boosts carrier mobility by 30-80%, making S/D epitaxy one of the most performance-critical process steps in FinFET and GAA manufacturing**.
**Why Epitaxial Source/Drain**
At 22 nm FinFET and beyond, conventional ion implantation cannot adequately dope the narrow fin source/drain regions:
- Fin width: 5-7 nm — ion implantation would amorphize the entire fin, and recrystallization of such narrow structures is poor.
- Epitaxial growth deposits pre-doped crystalline material with controlled composition, achieving both high doping concentrations (>10²¹ cm⁻³) and excellent crystal quality.
- Channel strain: SiGe S/D (PMOS) applies compressive strain to the channel, boosting hole mobility. Si:P S/D (NMOS) with higher lattice constant than relaxed Si can provide tensile strain.
**Selective Epitaxial Growth (SEG)**
S/D epi must grow only on exposed Si/SiGe surfaces, not on dielectric (SiO₂, SiN):
- **Growth Chemistry**: SiH₂Cl₂ or SiH₄ + GeH₄ + B₂H₆ (for SiGe:B), SiH₄ + PH₃ (for Si:P) at 550-700°C.
- **Selectivity**: HCl gas added as an etchant. HCl etches nuclei on dielectric surfaces faster than they form, while epitaxial growth on crystalline Si proceeds. Cl-based chemistry is inherently selective.
- **Pressure/Temperature**: 10-80 Torr, 550-680°C. Lower temperature: better selectivity but slower growth. Higher temperature: faster growth but reduced selectivity and profile control.
**PMOS SiGe:B Epitaxy**
- **Ge Content**: 30-55% (higher Ge = more compressive strain = more mobility enhancement, but also more defects from lattice mismatch).
- **Boron Doping**: 1-5 × 10²⁰ cm⁻³ in-situ (incorporated during growth). Contact resistance is a primary limiter — active B concentration must be maximized.
- **Shape Engineering**: Diamond-shaped faceted epi for planar/FinFET. The {111} facets provide merge between adjacent fins.
- **Sigma Cavity**: At some nodes, the Si in the S/D region is etched with a {111}-selective wet etch creating a sigma-shaped (Σ) recess that brings the SiGe stressor closer to the channel, increasing strain.
**NMOS Si:P Epitaxy**
- **Phosphorus Doping**: Target >3 × 10²¹ cm⁻³ for lowest contact resistance. Phosphorus has limited solid solubility in Si (~2 × 10²¹ at equilibrium), so metastable supersaturation techniques (low temperature growth + flash anneal) are used.
- **Si:C:P**: Adding ~1-2% carbon to Si:P creates tensile strain (C substitutional is smaller than Si). Used at some nodes for NMOS strain enhancement.
**GAA Nanosheet S/D Epi Challenges**
In GAA architectures, S/D epi must:
- Grow from multiple exposed nanosheet edges simultaneously.
- Merge between vertically stacked nanosheet layers into a continuous S/D region.
- Avoid void formation between nanosheet layers.
- Maintain homogeneous doping across the merged region.
The epi growth rate and facet control must be carefully optimized to achieve uniform merging without under-fill or over-growth.
S/D Epitaxy is **the doping and strain engineering workhorse of advanced CMOS** — the process that simultaneously delivers the extreme doping concentrations needed for low contact resistance and the precise lattice mismatch that creates the channel strain responsible for much of the performance gain at each new technology node.