source drain formation

**Source/Drain Formation** — creating the heavily doped regions that supply and collect carriers in a MOSFET, achieved through ion implantation and annealing. **Process Sequence** 1. **Halo/Pocket Implant**: Angled, opposite-type dopant near channel edges to control short-channel effects 2. **LDD (Lightly Doped Drain)**: Low-dose implant of same type as S/D. Reduces hot carrier injection 3. **Spacer Deposition**: Si3N4 spacers on gate sidewalls offset the heavy implant from the channel 4. **Heavy S/D Implant**: High-dose arsenic (NMOS) or boron (PMOS) to form low-resistance regions 5. **Activation Anneal**: RTA (1000-1050C, seconds) or laser spike anneal (milliseconds) to activate dopants while minimizing diffusion **Advanced Techniques** - **Raised S/D**: Epitaxially grow Si or SiGe above original surface to reduce series resistance - **SiGe S/D (PMOS)**: Compressive stress on channel boosts hole mobility by 25-50% - **SiC S/D (NMOS)**: Tensile stress enhances electron mobility - **In-situ doped epitaxy**: Avoids implant damage, provides abrupt junctions **S/D engineering** is critical — it determines both transistor speed (via resistance) and reliability (via junction quality).