strained silicon

Strained silicon applies mechanical stress to the transistor channel to enhance carrier mobility, improving drive current and performance without dimensional scaling. Physics: mechanical strain modifies the silicon crystal band structure—changes effective mass and scattering rates, increasing electron or hole mobility by 30-80%. Strain types: (1) Tensile strain—stretches Si lattice, improves electron mobility (NMOS); (2) Compressive strain—compresses Si lattice, improves hole mobility (PMOS). Strain techniques: (1) Embedded SiGe (eSiGe) source/drain—epitaxial SiGe in S/D regions creates uniaxial compressive stress on PMOS channel (introduced at 90nm); (2) Stress liner (CESL)—tensile Si₃N₄ liner over NMOS, compressive over PMOS (dual stress liner, DSL); (3) Stress memorization technique (SMT)—stress from amorphization/recrystallization during S/D anneal; (4) Strained SiGe channel—grow SiGe channel on Si for built-in compressive strain (PMOS); (5) Global strain—biaxial tensile Si on relaxed SiGe virtual substrate. Strain engineering by node: 90nm (eSiGe, CESL), 65/45nm (optimized eSiGe, DSL), 32/28nm (combined techniques), FinFET era (strained S/D epi on fins—SiGe for PMOS, Si:P for NMOS). Measurement: nano-beam diffraction (NBD), convergent beam electron diffraction (CBED), Raman spectroscopy. Challenges: strain relaxation during subsequent thermal processing, strain uniformity, strain loss in short channels. Strain engineering remains essential at every node—performance improvement equivalent to partial node scaling without lithography advances.