thermal tsv
**Thermal TSV** is a **dedicated through-silicon via filled with copper that serves exclusively as a vertical heat conduction path rather than an electrical signal carrier** — providing a low-thermal-resistance channel through stacked silicon dies to extract heat from buried layers in 3D-stacked packages, where the thermal conductivity of copper (400 W/mK) is 2.7× higher than silicon (148 W/mK), making thermal TSVs essential for managing hotspots and reducing peak temperatures in 3D ICs and HBM memory stacks.
**What Is a Thermal TSV?**
- **Definition**: A copper-filled via that passes through a silicon die from top to bottom, identical in fabrication to a signal TSV but not connected to any electrical circuit — its sole purpose is to conduct heat vertically from a hot region on one side of the die to a cooler surface or heat sink on the other side.
- **Dummy Via**: Thermal TSVs are sometimes called "dummy TSVs" because they carry no signal — they occupy silicon area that could otherwise be used for transistors or routing, representing a direct tradeoff between thermal performance and functional density.
- **Array Placement**: Thermal TSVs are typically placed in arrays directly above or below hotspot regions — a 10×10 array of 10 μm diameter TSVs at 50 μm pitch occupies 0.25 mm² but can reduce hotspot temperature by 10-15°C.
- **Keep-Out Zone**: Each TSV requires a keep-out zone (KOZ) around it where no transistors can be placed — due to mechanical stress from the copper-silicon CTE mismatch, the KOZ is typically 2-5 μm around each TSV, increasing the effective area cost.
**Why Thermal TSVs Matter**
- **3D Stack Cooling**: In 3D-stacked dies, interior layers have no direct path to the heat sink — thermal TSVs create artificial heat pipes through the silicon stack, reducing the thermal resistance from buried dies to the package surface by 20-40%.
- **Hotspot Management**: Thermal TSVs placed under hotspot regions provide targeted cooling — reducing peak temperature more effectively than increasing overall cooling capacity, because the problem is localized heat concentration, not total heat.
- **HBM Thermal Path**: HBM memory stacks use thermal TSVs alongside signal TSVs — the copper-filled vias help conduct heat from interior DRAM dies (which have no direct contact with the heat sink) to the top of the stack where the heat spreader makes contact.
- **Design Flexibility**: Thermal TSVs can be added to existing designs without changing the circuit — they are placed in unused silicon area (white space) between functional blocks, providing thermal improvement with minimal design disruption.
**Thermal TSV Design Parameters**
| Parameter | Typical Value | Impact |
|-----------|-------------|--------|
| Diameter | 5-20 μm | Larger = lower thermal resistance |
| Pitch | 30-100 μm | Tighter = better cooling, more area cost |
| Depth | 30-100 μm (die thickness) | Matches thinned die thickness |
| Fill Material | Copper (400 W/mK) | 2.7× better than silicon |
| Keep-Out Zone | 2-5 μm radius | Area overhead per TSV |
| Array Size | 10×10 to 50×50 | Larger arrays for bigger hotspots |
| Temp Reduction | 5-15°C per array | Depends on hotspot power density |
| Area Overhead | 1-5% of die area | Tradeoff with functional density |
**Thermal TSV vs. Signal TSV**
| Feature | Signal TSV | Thermal TSV |
|---------|-----------|-------------|
| Purpose | Electrical connection | Heat conduction |
| Connected to Circuit | Yes | No (dummy) |
| Placement | Fixed by circuit design | Flexible (white space) |
| Diameter | 5-10 μm | 10-20 μm (larger preferred) |
| Fill | Copper | Copper |
| Liner | SiO₂ + barrier | SiO₂ + barrier |
| Design Constraint | Signal integrity | Thermal optimization |
| Area Cost | Required for function | Pure overhead |
**Thermal TSVs are the essential heat management tool for 3D-stacked semiconductors** — providing dedicated copper heat pipes through silicon dies that reduce hotspot temperatures and thermal resistance in vertically integrated packages, enabling the high-power 3D stacking needed for HBM memory, stacked processors, and advanced heterogeneous integration.