via-middle tsv
**Via-Middle TSV** is the **industry-standard through-silicon via fabrication approach where TSVs are formed after front-end transistor fabrication (FEOL) but before back-end interconnect wiring (BEOL)** — combining the benefits of copper fill (low resistance) with minimal FEOL impact, and serving as the production technology for HBM memory stacks, TSMC CoWoS interposers, and virtually all commercial 3D integrated circuits.
**What Is Via-Middle TSV?**
- **Definition**: A TSV integration scheme where through-silicon vias are etched and filled with copper or tungsten after transistor fabrication is complete but before the multi-layer metal interconnect stack (BEOL) is built — the TSV is formed in the "middle" of the overall process flow.
- **Copper Fill**: Because FEOL high-temperature processing (> 1000°C) is already complete, copper can be used as the TSV fill material — providing 100-1000× lower resistance than the polysilicon required for via-first, enabling high-bandwidth, low-power vertical interconnects.
- **Moderate Depth**: TSVs are etched to a depth of 50-100 μm (the target thinned wafer thickness) rather than the full 775 μm — the wafer will be thinned from the backside later to reveal the TSV bottoms.
- **Industry Standard**: Via-middle is the dominant TSV approach in production — used by TSMC, Samsung, SK Hynix, Intel, and Micron for HBM, 3D NAND, and advanced logic 3D stacking.
**Why Via-Middle Matters**
- **Optimal Balance**: Via-middle provides the best tradeoff between TSV performance (copper fill), process risk (FEOL already complete), and manufacturing maturity (proven in high-volume production).
- **HBM Production**: Every HBM memory stack (HBM2E, HBM3, HBM3E) uses via-middle TSVs — SK Hynix, Samsung, and Micron collectively produce hundreds of millions of HBM dies annually with via-middle TSVs.
- **Low Resistance**: Copper-filled via-middle TSVs achieve < 50 mΩ per via — enabling the thousands of simultaneous data connections needed for HBM's 1024-bit wide memory interface.
- **Proven Reliability**: Via-middle TSVs have been in mass production since 2013 (HBM1) with demonstrated reliability through billions of thermal cycles and years of field operation.
**Via-Middle Process Flow**
- **Step 1 — FEOL Complete**: All transistors fabricated on standard 775 μm wafer — gate oxide, source/drain implants, silicide contacts, and contact-level tungsten plugs.
- **Step 2 — TSV Etch (DRIE)**: Deep reactive ion etch (Bosch process) creates high-aspect-ratio holes (5-10 μm diameter × 50-100 μm depth) through the silicon, stopping before reaching the wafer backside.
- **Step 3 — Liner Deposition**: SiO₂ insulation layer (100-500 nm) deposited by CVD to electrically isolate the TSV from the silicon substrate.
- **Step 4 — Barrier/Seed**: TaN/Ta barrier (10-30 nm) prevents copper diffusion into silicon; Cu seed layer (100-200 nm) enables electroplating.
- **Step 5 — Copper Electroplating**: Bottom-up copper fill using superfilling additives (accelerators, suppressors, levelers) to achieve void-free filling of high-aspect-ratio vias.
- **Step 6 — CMP**: Remove excess copper from the wafer surface, planarizing for subsequent BEOL processing.
- **Step 7 — BEOL**: Standard multi-layer metal interconnect fabrication proceeds on top of the TSV-containing wafer.
| Parameter | Typical Specification | Impact |
|-----------|---------------------|--------|
| TSV Diameter | 5-10 μm | Density vs. fill difficulty |
| TSV Depth | 50-100 μm | Thinned wafer thickness |
| Aspect Ratio | 5:1 - 10:1 | Etch and fill challenge |
| Fill Material | Copper (ECD) | < 50 mΩ resistance |
| Liner | SiO₂ (100-500 nm) | Isolation, capacitance |
| Barrier | TaN/Ta (10-30 nm) | Cu diffusion prevention |
| Pitch | 20-40 μm (HBM) | Interconnect density |
**Via-middle TSV is the proven production technology for 3D semiconductor integration** — forming copper-filled through-silicon vias after transistor fabrication to achieve low-resistance vertical interconnects without impacting device performance, serving as the manufacturing backbone for HBM memory stacks and every major commercial 3D integration platform.