wafer level packaging
**Wafer-Level Packaging (WLP)** is the **semiconductor packaging technology that completes all or most of the packaging process steps while dies are still in wafer form** — enabling the smallest possible package size (package footprint ≈ die footprint), lowest cost through wafer-level batch processing, and superior electrical performance by eliminating wire bonds and long package substrates. WLP has become the dominant packaging technology for smartphones, wearables, and IoT devices where compact form factor and low power are paramount.
**WLP Variants**
| Type | Description | Package Size | I/O Count |
|------|------------|-------------|----------|
| WLCSP (Fan-in) | Bumps placed only over die area | = Die size | Up to ~400 |
| FOWLP (Fan-out) | Reconstituted wafer; bumps extend beyond die | > Die size | 100–1000+ |
| WLCSP + RDL | Redistribution layer routes to finer/coarser pitch | = Die size | ~200–500 |
| EWLB (Fan-out) | Infineon fan-out variant | > Die size | 200–1000 |
**WLCSP (Fan-In) Process**
```
1. Wafer fab complete (transistors, metal layers done)
2. RDL (Redistribution Layer): Deposit polymer (PI) → Cu trace → reroute bond pads to larger pitch
3. UBM (Under Bump Metallization): TiW/Cu or Ti/Ni/Au pad for solder adhesion
4. Solder ball mount: Print/place solder balls (200–400 µm pitch)
5. Reflow: Balls form hemispherical bumps
6. Wafer singulation: Dicing → individual packages
7. Test: Final test before or after singulation
```
**FOWLP (Fan-Out Wafer-Level Packaging)**
- Dies are placed face-down on a temporary carrier → encapsulated in molding compound → reconstituted artificial wafer.
- RDL layers built on top → fan out interconnects beyond die edge → more I/Os possible.
- **Benefit**: Multiple dies can be integrated side-by-side in one package (2.5D-like without an expensive interposer).
- **Apple A-series**: First mass-market FOWLP at scale — InFO (Integrated Fan-Out) by TSMC since 2016.
**FOWLP Process Flow**
```
1. Singulate dies from wafer → test (known-good die)
2. Place dies face-down on temporary glass carrier
3. Mold with epoxy compound → cure
4. De-bond carrier → flip reconstituted wafer (dies now face up)
5. Build RDL layers (1–4 layers) on die surface + mold compound
6. Mount solder balls or copper pillars
7. Singulate → individual FOWLP packages
```
**Key Advantages vs. Wire Bond BGA**
| Metric | Wire Bond BGA | WLP/FOWLP |
|--------|-------------|----------|
| Package thickness | 0.8–2.0 mm | 0.35–0.8 mm |
| Inductance | 0.5–2 nH (wire) | 0.1–0.3 nH (RDL) |
| Thermal resistance | Higher (substrate barrier) | Lower (direct die exposure) |
| Cost (high volume) | Low | Very low (wafer-level batch) |
| Multi-die integration | Limited | Yes (FOWLP) |
**RDL (Redistribution Layer) Technology**
- Thin-film Cu/polymer layers (line/space: 2–10 µm) reroute die I/Os to larger ball pitch.
- 1–4 RDL layers for most WLCSP; 4–8 layers for advanced FOWLP.
- **Panel-level packaging**: Extend FOWLP to rectangular panels (600×600mm) → higher throughput, lower cost per unit.
**Applications**
- **Mobile SoC packaging**: Apple iPhone (TSMC InFO), Qualcomm Snapdragon (OSATS fan-out).
- **Power management ICs**: WLCSP dominates PMICs in smartphones.
- **RF modules**: FOWLP integrates PA + LNA + filters in one package.
- **IoT sensors**: WLCSP delivers minimum board space for MEMS + ASIC stacks.
Wafer-level packaging is **the packaging innovation that made the modern smartphone possible** — by packaging ICs at the wafer level with sub-millimeter thickness and ultra-short interconnects, WLP delivers the combination of small form factor, high electrical performance, and low cost that drives the entire mobile semiconductor ecosystem.