what is a wafer acceptance test
A wafer acceptance test, or WAT, is a standardized set of electrical measurements taken on special test structures scattered across a wafer to confirm the underlying fabrication process itself is running within spec, before any customer's actual chip designs on that wafer are even tested.
```flowchart
{
"rows": [
{ "type": "nodes", "items": [
{ "title": "Wafer completes fabrication", "sub": "chip designs are on it, but process health isn't yet confirmed", "tone": "neutral" }
]},
{ "type": "arrow" },
{ "type": "group", "title": "WAT measures dedicated test structures", "items": [
{ "title": "Transistor and interconnect parameters checked", "sub": "confirms the process itself, not the customer's design", "tone": "blue" }
]},
{ "type": "arrow" },
{ "type": "nodes", "items": [
{ "title": "Wafer accepted or flagged before further testing", "sub": "customer chip testing only proceeds on a healthy process", "tone": "green" }
]}
]
}
```
**WAT exists to answer a different question than testing a customer's actual chip design: is the underlying fabrication process itself healthy, independent of whatever specific design happened to be manufactured on this wafer?** Rather than relying solely on testing a customer's actual chip circuits, WAT measures dedicated test structures, typically placed in the scribe lines between chip dies, that are specifically designed to reveal core process parameters like transistor performance and interconnect resistance — giving a process-level health check that applies regardless of which specific chip design was manufactured.
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| Aspect | Customer chip test | Wafer acceptance test |
|---|---|---|
| What's measured | The customer's specific chip design | Dedicated process-monitoring test structures |
| What it confirms | Whether that particular design works | Whether the fabrication process itself is healthy |
| Location on wafer | The chip dies themselves | Scribe lines between dies |
| Typical timing | After WAT confirms process health | Before customer chip testing proceeds |
**WAT results are typically compared against tightly controlled statistical process limits, and a wafer failing WAT can be flagged or scrapped before any customer chip testing even begins.** Because WAT parameters are measured across essentially every production wafer, fabs maintain detailed statistical process control limits for each measured parameter, and a wafer whose WAT results fall outside those limits can be caught and addressed early, before time and resources are spent testing customer chip designs on a wafer with an underlying process problem.
**WAT data provides a continuous, standardized way to track a fab's process health and stability over time, independent of whatever specific chip designs happen to be running through the fab.** Because WAT test structures and measurements stay consistent across many different wafer lots and customer designs, WAT data gives fabs a long-term, apples-to-apples view of process stability that would be much harder to establish by comparing across different customers' unrelated chip designs alone.
**WAT specifically targets fundamental process parameters like transistor threshold voltage, drive current, and interconnect resistance, rather than complex functional behavior.** The dedicated test structures used in WAT are deliberately simple compared to a real chip design, since they're designed to isolate and measure specific fundamental electrical parameters cleanly — WAT is concerned with confirming the building blocks are within spec, not with verifying complex functional behavior, which is left to actual chip-level testing.
Read the wafer acceptance test through a foundation-inspection lens: before ever checking whether a specific finished chip design actually works, WAT checks whether the underlying fabrication process itself is sound — much like inspecting a building's foundation before worrying about whether any particular room inside it was built to plan.