ChipFoundryServices
⚡ From Planar NAND Arrays to Gate-All-Around Cylindrical Strings & Series Resistance Mitigation

Vertical NAND Strings & Multilayer Wordline Stacks University

The advanced engineering science of Vertical 3D NAND strings: series string transistor connectivity, cylindrical gate-all-around (GAA) electrostatics, thin-film hollow 'Macaroni' polycrystalline silicon channels, channel potential self-boosting, pass voltage ($V_{pass}$) optimization, and mutual cell crosstalk suppression.

7 Levels
Elementary to Fellow
21 Modules
Rigorous Curriculum
7 Sim Labs
Real-Time Engines
7 Diplomas
Industry Fellow Laureate
Academic Level 1 • Ages 6–10
Foundational Principles & 3D NAND Metaphors
Understand core principles, charge traps, and physical intuition.
Module 1.1

What is a Vertical NAND String?

Detailed engineering investigation of what is a vertical nand string? within advanced 3D NAND manufacturing architectures.

Process engineers must carefully optimize gas phase precursors, aspect ratio gradients, and electrostatic margins across multi-tier wordline stacks.

  • What is a Vertical NAND String?: Primary physical and material mechanism governing 3D NAND operation.
  • Process Window: Critical tolerances required for ultra-high-aspect-ratio (UHAR) 300mm wafer fabrication.
$$\text{String Capacity} = N_{WL} \text{ Cells} + \text{SGD} + \text{SGS} + \text{Dummy Gates}$$
Module 1.2

Stacking 100+ Memory Cells Upward

In-depth analysis of stacking 100+ memory cells upward and its direct impact on cell threshold voltage ($V_{th}$) stability and parasitic capacitance.

High-resolution cross-sectional STEM and automated optical scatterometry verify layer uniformity and defect suppression from deck top to bottom.

  • Stacking 100+ Memory Cells Upward: Essential engineering variable in cutting-edge 3D NAND memory generations.
  • Defect Screening: In-situ optical emission spectroscopy and multivariate control maintaining tight distribution limits.
$$\text{String Capacity} = N_{WL} \text{ Cells} + \text{SGD} + \text{SGS} + \text{Dummy Gates}$$
Module 1.3

The Common Source Line and Bitline Ends

Comprehensive evaluation of the common source line and bitline ends and strategic manufacturing roadmaps for high-capacity solid-state storage.

Integrating these principles into mass production ensures compliance with enterprise retention and endurance standards across extreme temperature regimes.

  • The Common Source Line and Bitline Ends: Key milestone enabling multi-terabit single-die storage density.
  • Commercial Verification: Validated through electrical test sort, high-voltage cycling, and thermal data retention stress.
$$\text{String Capacity} = N_{WL} \text{ Cells} + \text{SGD} + \text{SGS} + \text{Dummy Gates}$$
⚡ Interactive Laboratory L1
Level 1 Interactive Vertical NAND Strings & Multilayer Wordline Stacks University Simulator
Adjust key variables to simulate physical and chemical responses in vertical nand strings & multilayer wordline stacks university.
Process Precision Level50 %
Etch / Deposition Bias5 kV
REAL-TIME SIMULATION TELEMETRY
Interactive physics simulator running client-side transfer models, carrier drift-diffusion kinetics, and boundary potential solvers.
Critical Dimension (CD)
Nominal Spec
Profile Integrity
High Fidelity
🎓 Level 1 Examination
Level 1 Conceptual & Quantitative Mastery Assessment
In Vertical NAND Strings & Multilayer Wordline Stacks University, what is the primary role of What is a Vertical NAND String??
What physical challenge must be overcome when scaling Vertical NAND Strings & Multilayer Wordline Stacks University to 200+ layer architectures?
How is process compliance for The Common Source Line and Bitline Ends confirmed during high-volume manufacturing?

Level 1 Completed: Vertical NAND Strings & Multilayer Wordline Stacks University Foundations Certificate

Conferred by ChipFoundryServices OS for verified theoretical and practical mastery of Vertical NAND Strings & Multilayer Wordline Stacks University at Level 1.

Academic Level 2 • Ages 11–13
Architectural Stack Geometry & Strings
Explore vertical channels, wordline stacks, and circuit diagrams.
Module 2.1

The Cylindrical Gate-All-Around (GAA) Wrap

Detailed engineering investigation of the cylindrical gate-all-around (gaa) wrap within advanced 3D NAND manufacturing architectures.

Process engineers must carefully optimize gas phase precursors, aspect ratio gradients, and electrostatic margins across multi-tier wordline stacks.

  • The Cylindrical Gate-All-Around (GAA) Wrap: Primary physical and material mechanism governing 3D NAND operation.
  • Process Window: Critical tolerances required for ultra-high-aspect-ratio (UHAR) 300mm wafer fabrication.
$$W_{eff} = \pi \cdot D_{channel} \quad (\approx \pi \times 60\,\text{nm} \approx 188\,\text{nm})$$
Module 2.2

The Hollow Poly-Si Macaroni Tube

In-depth analysis of the hollow poly-si macaroni tube and its direct impact on cell threshold voltage ($V_{th}$) stability and parasitic capacitance.

High-resolution cross-sectional STEM and automated optical scatterometry verify layer uniformity and defect suppression from deck top to bottom.

  • The Hollow Poly-Si Macaroni Tube: Essential engineering variable in cutting-edge 3D NAND memory generations.
  • Defect Screening: In-situ optical emission spectroscopy and multivariate control maintaining tight distribution limits.
$$W_{eff} = \pi \cdot D_{channel} \quad (\approx \pi \times 60\,\text{nm} \approx 188\,\text{nm})$$
Module 2.3

How Current Flows Down the Pillar

Comprehensive evaluation of how current flows down the pillar and strategic manufacturing roadmaps for high-capacity solid-state storage.

Integrating these principles into mass production ensures compliance with enterprise retention and endurance standards across extreme temperature regimes.

  • How Current Flows Down the Pillar: Key milestone enabling multi-terabit single-die storage density.
  • Commercial Verification: Validated through electrical test sort, high-voltage cycling, and thermal data retention stress.
$$W_{eff} = \pi \cdot D_{channel} \quad (\approx \pi \times 60\,\text{nm} \approx 188\,\text{nm})$$
⚡ Interactive Laboratory L2
Level 2 Interactive Vertical NAND Strings & Multilayer Wordline Stacks University Simulator
Adjust key variables to simulate physical and chemical responses in vertical nand strings & multilayer wordline stacks university.
Process Precision Level50 %
Etch / Deposition Bias5 kV
REAL-TIME SIMULATION TELEMETRY
Interactive physics simulator running client-side transfer models, carrier drift-diffusion kinetics, and boundary potential solvers.
Critical Dimension (CD)
Nominal Spec
Profile Integrity
High Fidelity
🎓 Level 2 Examination
Level 2 Conceptual & Quantitative Mastery Assessment
In Vertical NAND Strings & Multilayer Wordline Stacks University, what is the primary role of The Cylindrical Gate-All-Around (GAA) Wrap?
What physical challenge must be overcome when scaling Vertical NAND Strings & Multilayer Wordline Stacks University to 200+ layer architectures?
How is process compliance for How Current Flows Down the Pillar confirmed during high-volume manufacturing?

Level 2 Completed: Vertical NAND Strings & Multilayer Wordline Stacks University Architecture & Circuitry Certificate

Conferred by ChipFoundryServices OS for verified theoretical and practical mastery of Vertical NAND Strings & Multilayer Wordline Stacks University at Level 2.

Academic Level 3 • Ages 14–18
Physical Chemistry, Etching & ALD Kinetics
Master reaction kinetics, gas-phase precursors, and high-aspect etching.
Module 3.1

Series Channel Resistance in Deep Strings

Detailed engineering investigation of series channel resistance in deep strings within advanced 3D NAND manufacturing architectures.

Process engineers must carefully optimize gas phase precursors, aspect ratio gradients, and electrostatic margins across multi-tier wordline stacks.

  • Series Channel Resistance in Deep Strings: Primary physical and material mechanism governing 3D NAND operation.
  • Process Window: Critical tolerances required for ultra-high-aspect-ratio (UHAR) 300mm wafer fabrication.
$$R_{string} = \sum_{i=1}^{N_{WL}} R_{cell,i} + R_{SGD} + R_{SGS} + R_{CSL}$$
Module 3.2

Current Continuity Along 128+ Tiers

In-depth analysis of current continuity along 128+ tiers and its direct impact on cell threshold voltage ($V_{th}$) stability and parasitic capacitance.

High-resolution cross-sectional STEM and automated optical scatterometry verify layer uniformity and defect suppression from deck top to bottom.

  • Current Continuity Along 128+ Tiers: Essential engineering variable in cutting-edge 3D NAND memory generations.
  • Defect Screening: In-situ optical emission spectroscopy and multivariate control maintaining tight distribution limits.
$$R_{string} = \sum_{i=1}^{N_{WL}} R_{cell,i} + R_{SGD} + R_{SGS} + R_{CSL}$$
Module 3.3

String Drive Current ($I_{cell}$) Limits

Comprehensive evaluation of string drive current ($i_{cell}$) limits and strategic manufacturing roadmaps for high-capacity solid-state storage.

Integrating these principles into mass production ensures compliance with enterprise retention and endurance standards across extreme temperature regimes.

  • String Drive Current ($I_{cell}$) Limits: Key milestone enabling multi-terabit single-die storage density.
  • Commercial Verification: Validated through electrical test sort, high-voltage cycling, and thermal data retention stress.
$$R_{string} = \sum_{i=1}^{N_{WL}} R_{cell,i} + R_{SGD} + R_{SGS} + R_{CSL}$$
⚡ Interactive Laboratory L3
Level 3 Interactive Vertical NAND Strings & Multilayer Wordline Stacks University Simulator
Adjust key variables to simulate physical and chemical responses in vertical nand strings & multilayer wordline stacks university.
Process Precision Level50 %
Etch / Deposition Bias5 kV
REAL-TIME SIMULATION TELEMETRY
Interactive physics simulator running client-side transfer models, carrier drift-diffusion kinetics, and boundary potential solvers.
Critical Dimension (CD)
Nominal Spec
Profile Integrity
High Fidelity
🎓 Level 3 Examination
Level 3 Conceptual & Quantitative Mastery Assessment
In Vertical NAND Strings & Multilayer Wordline Stacks University, what is the primary role of Series Channel Resistance in Deep Strings?
What physical challenge must be overcome when scaling Vertical NAND Strings & Multilayer Wordline Stacks University to 200+ layer architectures?
How is process compliance for String Drive Current ($I_{cell}$) Limits confirmed during high-volume manufacturing?

Level 3 Completed: Vertical NAND Strings & Multilayer Wordline Stacks University Chemical & Physical Kinetics Certificate

Conferred by ChipFoundryServices OS for verified theoretical and practical mastery of Vertical NAND Strings & Multilayer Wordline Stacks University at Level 3.

Academic Level 4 • Undergraduate Lower-Division
Solid-State Physics & Carrier Transport
Analyze tunneling quantum mechanics, Poisson band bending, and space charge.
Module 4.1

Channel Potential Self-Boosting Physics

Detailed engineering investigation of channel potential self-boosting physics within advanced 3D NAND manufacturing architectures.

Process engineers must carefully optimize gas phase precursors, aspect ratio gradients, and electrostatic margins across multi-tier wordline stacks.

  • Channel Potential Self-Boosting Physics: Primary physical and material mechanism governing 3D NAND operation.
  • Process Window: Critical tolerances required for ultra-high-aspect-ratio (UHAR) 300mm wafer fabrication.
$$V_{ch,boost} = V_{inital} + \sum \frac{C_{WL-ch}}{C_{total}} (V_{pass} - V_{low})$$
Module 4.2

Inhibited Cell Program Disturb Mitigation

In-depth analysis of inhibited cell program disturb mitigation and its direct impact on cell threshold voltage ($V_{th}$) stability and parasitic capacitance.

High-resolution cross-sectional STEM and automated optical scatterometry verify layer uniformity and defect suppression from deck top to bottom.

  • Inhibited Cell Program Disturb Mitigation: Essential engineering variable in cutting-edge 3D NAND memory generations.
  • Defect Screening: In-situ optical emission spectroscopy and multivariate control maintaining tight distribution limits.
$$V_{ch,boost} = V_{inital} + \sum \frac{C_{WL-ch}}{C_{total}} (V_{pass} - V_{low})$$
Module 4.3

Pass Voltage ($V_{pass}$) Window Optimization

Comprehensive evaluation of pass voltage ($v_{pass}$) window optimization and strategic manufacturing roadmaps for high-capacity solid-state storage.

Integrating these principles into mass production ensures compliance with enterprise retention and endurance standards across extreme temperature regimes.

  • Pass Voltage ($V_{pass}$) Window Optimization: Key milestone enabling multi-terabit single-die storage density.
  • Commercial Verification: Validated through electrical test sort, high-voltage cycling, and thermal data retention stress.
$$V_{ch,boost} = V_{inital} + \sum \frac{C_{WL-ch}}{C_{total}} (V_{pass} - V_{low})$$
⚡ Interactive Laboratory L4
Level 4 Interactive Vertical NAND Strings & Multilayer Wordline Stacks University Simulator
Adjust key variables to simulate physical and chemical responses in vertical nand strings & multilayer wordline stacks university.
Process Precision Level50 %
Etch / Deposition Bias5 kV
REAL-TIME SIMULATION TELEMETRY
Interactive physics simulator running client-side transfer models, carrier drift-diffusion kinetics, and boundary potential solvers.
Critical Dimension (CD)
Nominal Spec
Profile Integrity
High Fidelity
🎓 Level 4 Examination
Level 4 Conceptual & Quantitative Mastery Assessment
In Vertical NAND Strings & Multilayer Wordline Stacks University, what is the primary role of Channel Potential Self-Boosting Physics?
What physical challenge must be overcome when scaling Vertical NAND Strings & Multilayer Wordline Stacks University to 200+ layer architectures?
How is process compliance for Pass Voltage ($V_{pass}$) Window Optimization confirmed during high-volume manufacturing?

Level 4 Completed: Vertical NAND Strings & Multilayer Wordline Stacks University Solid-State Physics Certificate

Conferred by ChipFoundryServices OS for verified theoretical and practical mastery of Vertical NAND Strings & Multilayer Wordline Stacks University at Level 4.

Academic Level 5 • Undergraduate Upper-Division
Unit Process Integration & 3D Deck Scaling
Examine replacement-gate processing, stress balancing, and TCAD simulations.
Module 5.1

Cell-to-Cell Interference in Vertical Strings

Detailed engineering investigation of cell-to-cell interference in vertical strings within advanced 3D NAND manufacturing architectures.

Process engineers must carefully optimize gas phase precursors, aspect ratio gradients, and electrostatic margins across multi-tier wordline stacks.

  • Cell-to-Cell Interference in Vertical Strings: Primary physical and material mechanism governing 3D NAND operation.
  • Process Window: Critical tolerances required for ultra-high-aspect-ratio (UHAR) 300mm wafer fabrication.
$$C_{cell-cell} = \frac{\epsilon_{spacer} A_{overlap}}{T_{spacer}} \implies \text{Z-Pitch Control}$$
Module 5.2

Z-Pitch Scaling vs Parasitic Capacitance

In-depth analysis of z-pitch scaling vs parasitic capacitance and its direct impact on cell threshold voltage ($V_{th}$) stability and parasitic capacitance.

High-resolution cross-sectional STEM and automated optical scatterometry verify layer uniformity and defect suppression from deck top to bottom.

  • Z-Pitch Scaling vs Parasitic Capacitance: Essential engineering variable in cutting-edge 3D NAND memory generations.
  • Defect Screening: In-situ optical emission spectroscopy and multivariate control maintaining tight distribution limits.
$$C_{cell-cell} = \frac{\epsilon_{spacer} A_{overlap}}{T_{spacer}} \implies \text{Z-Pitch Control}$$
Module 5.3

Back-Gate Coupling and Tapered Pillar CD

Comprehensive evaluation of back-gate coupling and tapered pillar cd and strategic manufacturing roadmaps for high-capacity solid-state storage.

Integrating these principles into mass production ensures compliance with enterprise retention and endurance standards across extreme temperature regimes.

  • Back-Gate Coupling and Tapered Pillar CD: Key milestone enabling multi-terabit single-die storage density.
  • Commercial Verification: Validated through electrical test sort, high-voltage cycling, and thermal data retention stress.
$$C_{cell-cell} = \frac{\epsilon_{spacer} A_{overlap}}{T_{spacer}} \implies \text{Z-Pitch Control}$$
⚡ Interactive Laboratory L5
Level 5 Interactive Vertical NAND Strings & Multilayer Wordline Stacks University Simulator
Adjust key variables to simulate physical and chemical responses in vertical nand strings & multilayer wordline stacks university.
Process Precision Level50 %
Etch / Deposition Bias5 kV
REAL-TIME SIMULATION TELEMETRY
Interactive physics simulator running client-side transfer models, carrier drift-diffusion kinetics, and boundary potential solvers.
Critical Dimension (CD)
Nominal Spec
Profile Integrity
High Fidelity
🎓 Level 5 Examination
Level 5 Conceptual & Quantitative Mastery Assessment
In Vertical NAND Strings & Multilayer Wordline Stacks University, what is the primary role of Cell-to-Cell Interference in Vertical Strings?
What physical challenge must be overcome when scaling Vertical NAND Strings & Multilayer Wordline Stacks University to 200+ layer architectures?
How is process compliance for Back-Gate Coupling and Tapered Pillar CD confirmed during high-volume manufacturing?

Level 5 Completed: Vertical NAND Strings & Multilayer Wordline Stacks University Process Integration Mastery Certificate

Conferred by ChipFoundryServices OS for verified theoretical and practical mastery of Vertical NAND Strings & Multilayer Wordline Stacks University at Level 5.

Academic Level 6 • Graduate / Master's
Quantum Confinement & Stochastic Reliability
Investigate interface traps, Fowler-Nordheim kinematics, and retention loss.
Module 6.1

Grain Boundary Scattering in Poly-Si Channels

Detailed engineering investigation of grain boundary scattering in poly-si channels within advanced 3D NAND manufacturing architectures.

Process engineers must carefully optimize gas phase precursors, aspect ratio gradients, and electrostatic margins across multi-tier wordline stacks.

  • Grain Boundary Scattering in Poly-Si Channels: Primary physical and material mechanism governing 3D NAND operation.
  • Process Window: Critical tolerances required for ultra-high-aspect-ratio (UHAR) 300mm wafer fabrication.
$$\mu_{poly} = \mu_0 \exp\left(-\frac{q V_B}{k_B T}\right) \quad (V_B = \text{Barrier Height})$$
Module 6.2

Hydrogen High-Pressure Annealing for Mobility

In-depth analysis of hydrogen high-pressure annealing for mobility and its direct impact on cell threshold voltage ($V_{th}$) stability and parasitic capacitance.

High-resolution cross-sectional STEM and automated optical scatterometry verify layer uniformity and defect suppression from deck top to bottom.

  • Hydrogen High-Pressure Annealing for Mobility: Essential engineering variable in cutting-edge 3D NAND memory generations.
  • Defect Screening: In-situ optical emission spectroscopy and multivariate control maintaining tight distribution limits.
$$\mu_{poly} = \mu_0 \exp\left(-\frac{q V_B}{k_B T}\right) \quad (V_B = \text{Barrier Height})$$
Module 6.3

TCAD Cylindrical Non-Equilibrium Solvers

Comprehensive evaluation of tcad cylindrical non-equilibrium solvers and strategic manufacturing roadmaps for high-capacity solid-state storage.

Integrating these principles into mass production ensures compliance with enterprise retention and endurance standards across extreme temperature regimes.

  • TCAD Cylindrical Non-Equilibrium Solvers: Key milestone enabling multi-terabit single-die storage density.
  • Commercial Verification: Validated through electrical test sort, high-voltage cycling, and thermal data retention stress.
$$\mu_{poly} = \mu_0 \exp\left(-\frac{q V_B}{k_B T}\right) \quad (V_B = \text{Barrier Height})$$
⚡ Interactive Laboratory L6
Level 6 Interactive Vertical NAND Strings & Multilayer Wordline Stacks University Simulator
Adjust key variables to simulate physical and chemical responses in vertical nand strings & multilayer wordline stacks university.
Process Precision Level50 %
Etch / Deposition Bias5 kV
REAL-TIME SIMULATION TELEMETRY
Interactive physics simulator running client-side transfer models, carrier drift-diffusion kinetics, and boundary potential solvers.
Critical Dimension (CD)
Nominal Spec
Profile Integrity
High Fidelity
🎓 Level 6 Examination
Level 6 Conceptual & Quantitative Mastery Assessment
In Vertical NAND Strings & Multilayer Wordline Stacks University, what is the primary role of Grain Boundary Scattering in Poly-Si Channels?
What physical challenge must be overcome when scaling Vertical NAND Strings & Multilayer Wordline Stacks University to 200+ layer architectures?
How is process compliance for TCAD Cylindrical Non-Equilibrium Solvers confirmed during high-volume manufacturing?

Level 6 Completed: Vertical NAND Strings & Multilayer Wordline Stacks University Advanced Quantum Transport Certificate

Conferred by ChipFoundryServices OS for verified theoretical and practical mastery of Vertical NAND Strings & Multilayer Wordline Stacks University at Level 6.

Academic Level 7 • PhD & Distinguished Fellow
Frontier 300+ Layer Scaling & Industry Honors
Evaluate atomic-scale physical limits, direct wafer bonding, and Fellow honors.
Module 7.1

Monolithic Single-Crystal Recrystallization

Detailed engineering investigation of monolithic single-crystal recrystallization within advanced 3D NAND manufacturing architectures.

Process engineers must carefully optimize gas phase precursors, aspect ratio gradients, and electrostatic margins across multi-tier wordline stacks.

  • Monolithic Single-Crystal Recrystallization: Primary physical and material mechanism governing 3D NAND operation.
  • Process Window: Critical tolerances required for ultra-high-aspect-ratio (UHAR) 300mm wafer fabrication.
$$I_{string,on} > 40\,\text{nA at } N_{WL} = 256 \text{ Layers}$$
Module 7.2

Zero-Resistance Superconducting Wordline Buses

In-depth analysis of zero-resistance superconducting wordline buses and its direct impact on cell threshold voltage ($V_{th}$) stability and parasitic capacitance.

High-resolution cross-sectional STEM and automated optical scatterometry verify layer uniformity and defect suppression from deck top to bottom.

  • Zero-Resistance Superconducting Wordline Buses: Essential engineering variable in cutting-edge 3D NAND memory generations.
  • Defect Screening: In-situ optical emission spectroscopy and multivariate control maintaining tight distribution limits.
$$I_{string,on} > 40\,\text{nA at } N_{WL} = 256 \text{ Layers}$$
Module 7.3

Distinguished Fellow 3D String Laureate

Comprehensive evaluation of distinguished fellow 3d string laureate and strategic manufacturing roadmaps for high-capacity solid-state storage.

Integrating these principles into mass production ensures compliance with enterprise retention and endurance standards across extreme temperature regimes.

  • Distinguished Fellow 3D String Laureate: Key milestone enabling multi-terabit single-die storage density.
  • Commercial Verification: Validated through electrical test sort, high-voltage cycling, and thermal data retention stress.
$$I_{string,on} > 40\,\text{nA at } N_{WL} = 256 \text{ Layers}$$
⚡ Interactive Laboratory L7
Level 7 Interactive Vertical NAND Strings & Multilayer Wordline Stacks University Simulator
Adjust key variables to simulate physical and chemical responses in vertical nand strings & multilayer wordline stacks university.
Process Precision Level50 %
Etch / Deposition Bias5 kV
REAL-TIME SIMULATION TELEMETRY
Interactive physics simulator running client-side transfer models, carrier drift-diffusion kinetics, and boundary potential solvers.
Critical Dimension (CD)
Nominal Spec
Profile Integrity
High Fidelity
🎓 Level 7 Examination
Level 7 Conceptual & Quantitative Mastery Assessment
In Vertical NAND Strings & Multilayer Wordline Stacks University, what is the primary role of Monolithic Single-Crystal Recrystallization?
What physical challenge must be overcome when scaling Vertical NAND Strings & Multilayer Wordline Stacks University to 200+ layer architectures?
How is process compliance for Distinguished Fellow 3D String Laureate confirmed during high-volume manufacturing?

Level 7 Completed: Vertical NAND Strings & Multilayer Wordline Stacks University Distinguished Fellow Honors

Conferred by ChipFoundryServices OS for verified theoretical and practical mastery of Vertical NAND Strings & Multilayer Wordline Stacks University at Level 7.

🏅
Distinguished Fellow in 3D String Electrostatics, Macaroni Channels & Multi-Layer Stacks
Highest academic honor conferred by ChipFoundryServices OS for demonstrated mastery across all 7 curriculum tiers, interactive simulation laboratories, and verified examination standards.