255 technical terms and definitions
positive negative photoresist, chemically amplified resist, euv photoresist development, photoresist processing lithography
Photoresist chemistry and track coat-bake-develop processing constitute the photochemical foundation of semiconductor patterning, converting aerial optical and extreme ultraviolet…
chemically amplified resist, euv photoresist, resist development process, dry resist metal oxide
Photoresist chemistry and track coat-bake-develop processing constitute the photochemical foundation of semiconductor patterning, converting aerial optical and extreme ultraviolet…
euv photoresist, chemically amplified resist, metal oxide resist mor, resist sensitivity resolution
Photoresist chemistry and track coat-bake-develop processing constitute the photochemical foundation of semiconductor patterning, converting aerial optical and extreme ultraviolet…
Photovoltaics: Semiconductor Junctions, Solar Cell Physics, and System Design Photovoltaic (PV) energy conversion transforms solar radiation directly into electricity via…
autonomous pd, machine learning pd, ml placement, ai eda, ml chip design
Machine Learning in Physical Design (AI-EDA) is the application of neural networks, reinforcement learning, and other ML techniques to accelerate and improve placement, routing…
block placement chip, macro placement, floorplan optimization, die area utilization
Chip Floorplanning is the critical early-stage physical design activity that determines the spatial arrangement of major functional blocks (hard macros, soft macros, memory…
chip floorplan methodology, block placement floorplan, floorplan power planning, hierarchical floorplanning
Physical Design Floorplanning is the critical early-stage physical implementation step that defines the chip's spatial organization by determining die size, placing hard macro…
block level pnr, top level integration, chip assembly
Hierarchical Physical Design is the divide-and-conquer methodology for implementing large SoCs where the chip is partitioned into independently designed blocks (macros/partitions)…
ring oscillator puf, sram puf bit, hardware fingerprint chip, puf authentication security
Physical Unclonable Functions (PUF) are a hardware security primitive that exploits manufacturing variations to generate unique, unpredictable, and unclonable per-chip secrets…
physical vapor, deposition process modeling, ml pvd, physical vapor deposition, vapor deposition process, vapor deposition, deposition process, process modeling
Physical Vapor Deposition Process Modeling Introduction & Motivation Predicting PVD process outcomes through ML accelerates film deposition development for coatings, electronics…
physical vapor deposition sputtering rate prediction, physical vapor deposition, vapor deposition sputtering, deposition sputtering rate, sputtering rate prediction
Physical Vapor Deposition Sputtering Rate Prediction with Machine Learning Introduction & Motivation Physical Vapor Deposition Sputtering Rate Prediction with Machine Learning…
physics modeling, differential equations, semiconductor physics, device physics, transport equations, heat transfer equations, process modeling, pde semiconductor
Physics-based semiconductor modeling converts conservation laws, material relations, geometry, and operating conditions into a boundary-value or initial-boundary-value problem…
piezoelectric mems actuator fabrication yield prediction machine learning, piezoelectric mems, actuator fabrication yield, mems, piezoelectric mems actuator
Piezoelectric MEMS Actuator Fabrication Yield Prediction with Machine Learning Introduction & Motivation Piezoelectric MEMS Actuator Fabrication Yield Prediction with Machine…
piezoresponse force microscopy, pfm, metrology
Piezoresponse Force Microscopy (PFM) is a contact-mode scanning probe technique that maps the local piezoelectric response of a material by applying an AC voltage through…
pin diode rf switch, pin diode photodetector, pin forward bias minority carrier, pin variable resistor
PIN Diode is the p-i-n junction with intrinsic (i) layer enabling efficient photodetection and RF switching through minority carrier storage and variable resistance under forward…
pga, packaging
Pin grid array is the package architecture with pins arranged in a two-dimensional grid on the package underside for high pin-count connectivity - it supports dense interconnect…
lithography pitch, contacted poly pitch, cpp, minimum metal pitch, mmp, feature pitch, pattern pitch, semiconductor pitch, node scaling, lithography
Lithography pitch is the fundamental center-to-center distance between repeating identical features on a semiconductor wafer, defining the ultimate packing density, interconnect…
advanced packaging
Pitch Scaling in Advanced Packaging is the progressive reduction of interconnect pitch (center-to-center distance between adjacent connections) between stacked dies or between die…
hoerni 1959 lateral diffusion insight surface junction, planar transistor 1959 junction under oxide recognition, silicon planar 1959 realization not new fabrication technique
Recognize That the Masking Oxide Already Covered the Junction the Whole Time: The Insight, Not the Material 1. Why the Lateral Diffusion Everyone Already Knew About Was the Whole…
hoerni 1959 contact window margin lateral diffusion design, planar transistor 1959 window inside diffused region oxide intact, silicon planar 1959 reuses photolithography new purpose
Open Small Contact Windows Through the Oxide by Photolithography: A New Reason for an Old Window 1. Why This Window Serves a Completely Different Purpose Than Every Earlier One…
hoerni 1959 metal etch undercut gap base emitter short, planar transistor 1959 second mask aluminum interconnect lines, silicon planar 1959 metal patterned not semiconductor
Pattern the Metal Into Interconnect Lines by a Second Photolithographic Mask: The Same Undercut, a New Way to Fail 1. Why the Gap Between Two Contacts Now Carries the Risk…
contact mask aligner equipment for 1959 photolithography, alignment tolerance between contact window and metal mask
Align the Second Mask to the First by Hand Under a Microscope: The Equipment Behind Step 3 and Step 6's Two Photographic Steps 1. Why Two Photolithographic Masks Only Work…
jean hoerni planar process patent application 1959, fairchild semiconductor planar process patent claim scope
File the Patent on the Step This Series Refused to Take: Hoerni's Claim, Not Just His Idea 1. Why the Insight at Step 1 and Step 2 Needed a Name and a Filing Date, Not Just…
planar process transistor, oxide masking photolithography diffusion, hoerni planar process, junction termination under oxide
The Planar Process: Oxide Masking, Lateral Patterning & Why the Junction Finally Went Under Glass Every process this lineage has covered so far — point-contact whiskers, alloy…
plasma process, semiconductor plasma, plasma processes
A semiconductor plasma is a weakly ionized gas where fewer than 1 in 300 particles carry charge — yet those few charged particles control 40–50% of all processing steps in…
advanced packaging
Plasma-Activated Bonding (PAB) is a surface treatment technique that uses plasma exposure to dramatically enhance direct wafer bonding strength — breaking surface bonds…
plasma chamber seasoning and first wafer effect mitigation with machine learning, plasma chamber seasoning first wafer effect mitigation machine learning, se
Plasma Chamber Seasoning and First-Wafer Effect Mitigation with Machine Learning Introduction & Motivation Plasma Chamber Seasoning and First-Wafer Effect Mitigation with Machine…
stealth dicing alternative, dry dicing wafer, low damage singulation, wafer singulation plasma
Plasma Dicing Technology is the dry wafer singulation method that etches streets instead of mechanically sawing dies. What It Covers Core concept: reduces chipping and particle…
PECVD, plasma enhanced chemical vapor deposition, PECVD silicon nitride, low temperature CVD
Plasma-enhanced chemical vapor deposition. uses an RF or microwave plasma to dissociate precursor gases and create reactive radicals, enabling film formation at lower substrate…
Active Learning for Plasma Etch Chambers Active Learning for Plasma Etch Chambers Introduction Active Learning for Plasma Etch Chambers is an engineering workflow for anisotropic…
Anomaly Detection for Plasma Etch Chambers Anomaly Detection for Plasma Etch Chambers Introduction Anomaly Detection for Plasma Etch Chambers is an engineering workflow…
Bayesian Parameter Estimation for Plasma Etch Chambers Bayesian Parameter Estimation for Plasma Etch Chambers Introduction Bayesian Parameter Estimation for Plasma Etch Chambers…
Causal Process Modeling for Plasma Etch Chambers Causal Process Modeling for Plasma Etch Chambers Introduction Causal Process Modeling for Plasma Etch Chambers is an engineering…
Chamber Matching for Plasma Etch Chambers Chamber Matching for Plasma Etch Chambers Introduction Chamber Matching for Plasma Etch Chambers is an engineering workflow…
Closed-Loop Yield Learning for Plasma Etch Chambers Closed-Loop Yield Learning for Plasma Etch Chambers Introduction Closed-Loop Yield Learning for Plasma Etch Chambers is…
Contamination Monitoring for Plasma Etch Chambers Contamination Monitoring for Plasma Etch Chambers Introduction Contamination Monitoring for Plasma Etch Chambers is…
Cost and Cycle-Time Optimization for Plasma Etch Chambers Cost and Cycle-Time Optimization for Plasma Etch Chambers Introduction Cost and Cycle-Time Optimization for Plasma Etch…
Critical Dimension Prediction for Plasma Etch Chambers Critical Dimension Prediction for Plasma Etch Chambers Introduction Critical Dimension Prediction for Plasma Etch Chambers…
Defect Excursion Detection for Plasma Etch Chambers Defect Excursion Detection for Plasma Etch Chambers Introduction Defect Excursion Detection for Plasma Etch Chambers is…
Design of Experiments for Plasma Etch Chambers Design of Experiments for Plasma Etch Chambers Introduction Design of Experiments for Plasma Etch Chambers is an engineering…
Digital Twin Calibration for Plasma Etch Chambers Digital Twin Calibration for Plasma Etch Chambers Introduction Digital Twin Calibration for Plasma Etch Chambers is…
Edge AI Deployment for Plasma Etch Chambers Edge AI Deployment for Plasma Etch Chambers Introduction Edge AI Deployment for Plasma Etch Chambers is an engineering workflow…
Endpoint Detection for Plasma Etch Chambers Endpoint Detection for Plasma Etch Chambers Introduction Endpoint Detection for Plasma Etch Chambers is an engineering workflow…
Equipment Health Monitoring for Plasma Etch Chambers Equipment Health Monitoring for Plasma Etch Chambers Introduction Equipment Health Monitoring for Plasma Etch Chambers is…
Fault Detection and Classification for Plasma Etch Chambers Fault Detection and Classification for Plasma Etch Chambers Introduction Fault Detection and Classification for Plasma…
Federated Learning for Plasma Etch Chambers Federated Learning for Plasma Etch Chambers Introduction Federated Learning for Plasma Etch Chambers is an engineering workflow…
Film Thickness Control for Plasma Etch Chambers Film Thickness Control for Plasma Etch Chambers Introduction Film Thickness Control for Plasma Etch Chambers is an engineering…
Multi-Objective Optimization for Plasma Etch Chambers Multi-Objective Optimization for Plasma Etch Chambers Introduction Multi-Objective Optimization for Plasma Etch Chambers is…
Overlay Error Correction for Plasma Etch Chambers Overlay Error Correction for Plasma Etch Chambers Introduction Overlay Error Correction for Plasma Etch Chambers is…
Particle Source Attribution for Plasma Etch Chambers Particle Source Attribution for Plasma Etch Chambers Introduction Particle Source Attribution for Plasma Etch Chambers is…