3,526 technical terms and definitions
25d packaging, 2.5d, 2.5d packaging, advanced packaging 25d, silicon interposer packaging, cowos
Interposers are the substrates that carry 2.5D integration: a die-to-die wiring layer dense enough to route thousands of connections between chiplets that sit side by side.…
materials, semiconductor, MoS2, WSe2, graphene
2D Materials in Semiconductors: MoS2, WSe2, and Graphene is atomically-thin layered materials exhibiting unique electronic properties enabling transistors, optoelectronic devices…
scm profiling, ssrm metrology
Two-Dimensional Dopant Profiling is a metrology technique that maps dopant concentration across both depth and lateral dimensions in semiconductor structures. What Is 2D Dopant…
transition metal dichalcogenide, tmd monolayer transistor, mos2 channel transistor, 2d semiconductor device
2D Semiconductor Materials (MoS₂/TMDs) is the family of transition metal dichalcogenide crystals with monolayer thickness exhibiting direct bandgaps and strong light-matter…
mos2 transistor fabrication, molybdenum disulfide, mos2, tmd fet, tmdc channel devices, 2d material transfer, 2d heterostructure integration
2D Material Transistors are the post-silicon device concept using atomically-thin layered semiconductors (MoS₂, WSe₂, black phosphorus) as channel materials — providing ultimate…
3d, metrology
3D AFM is an advanced atomic force microscopy technique that measures the three-dimensional profile of high-aspect-ratio semiconductor structures — going beyond conventional…
3d chip stacking and integration, 3d chip stacking, chip stacking integration, 3d chip, chip stacking, stacking integration
3D Chip Stacking and Integration Introduction & Motivation 3D Chip Stacking and Integration addresses a central problem in chip-architecture process control…
3D Heterogeneous Packaging, Interposers, TSVs, Hybrid Bonding, and Cryogenic Quantum Co-Integration 1. Why packaging now limits quantum scaling A superconducting quantum processor…
advanced packaging
Advanced packaging is the set of technologies that connect, protect and cool silicon after it leaves the fab. It has moved from a cost-driven back-end afterthought to a primary…
nand string architecture, charge trap flash memory, 3d nand layer count, nand vertical channel
3D NAND flash is the memory architecture that escapes planar scaling limits by stacking hundreds of storage layers vertically — each layer is a word-line (gate) wrapping…
3d ic tsv chiplet stack, logic memory stacking, 3d power delivery 3d, 3d thermal management stacked, hbm
High-bandwidth memory (HBM) is DRAM stacked vertically and connected to its host through an interface thousands of bits wide, running beside the processor on an interposer rather…
3d chip stacking and thermal coupling between layers, 3d chip stacking, chip stacking thermal, stacking thermal coupling, thermal coupling between, coupling between layers, 3d chip
3D Chip Stacking and Thermal Coupling Between Layers Introduction & Motivation 3D Chip Stacking and Thermal Coupling Between Layers addresses a central problem in thermal process…
3d, advanced packaging
3D Stacking via Bonding is the process of vertically integrating multiple semiconductor dies or wafers by bonding them face-to-face or face-to-back — creating three-dimensional…
4d stem, four-dimensional stem, four dimensional scanning transmission electron microscopy, pixelated stem, nanobeam diffraction 4d-stem, semiconductor strain mapping 4d-stem
Conventional STEM turns the signal arriving at a detector into one number at each probe position. That number may form an excellent bright-field, annular dark-field, or high-angle…
first principles simulation, density functional theory, quantum materials modeling, electronic structure calculation, dft semiconductor
Etch Plasma–Surface Ab Initio Molecular Dynamics (AIMD) Modeling follows atomic trajectories while recomputing electronic-structure forces from first principles at every time…
metrology
Aberration-Corrected TEM is a TEM equipped with hardware correctors (multipole lens systems) that eliminate spherical and chromatic aberrations — pushing the resolution limit…
metrology
Accuracy in metrology is the closeness of a measured value to the true or reference value of the quantity being measured — the fundamental property that determines whether…
interposer, chiplet, integration, routing
Active Interposer Design Integration is a silicon substrate containing embedded logic, routing resources, and power management circuits that actively orchestrates communication…
adaptive metrology sampling plan optimization machine learning, adaptive metrology, sampling plan optimization, adaptive metrology sampling plan optimization
Adaptive Metrology Sampling Plan Optimization with Machine Learning Introduction & Motivation Adaptive Metrology Sampling Plan Optimization with Machine Learning addresses…
advanced packaging
Adhesive Bonding is a wafer-level bonding technique that uses polymer adhesive layers to join two substrates — offering the lowest bonding temperature (< 200°C), highest…
dram capacitor technology, dram cell architecture, high k dram capacitor, dram buried wordline
High-bandwidth memory (HBM) is DRAM stacked vertically and connected to its host through an interface thousands of bits wide, running beside the processor on an interposer rather…
aib, advanced packaging
Advanced Interface Bus (AIB) is an open-source die-to-die interconnect standard originally developed by Intel and released under the DARPA CHIPS program — providing a parallel…
193nm immersion lithography, immersion scanner resolution, pellicle lithography, lithography overlay
193nm Immersion Lithography is the workhorse patterning technology that has defined semiconductor manufacturing from the 45nm node through today's most advanced EUV-assisted nodes…
photomask fabrication process, mask blank defect, pellicle euv mask, reticle enhancement technique
Photomask fabrication, phase-shift mask engineering, and nanoscopic defect repair constitute the foundational master-patterning technologies that enable optical projection…
CD-SEM, scatterometry, OCD, critical dimension measurement
Spectroscopic ellipsometry and inline optical wafer metrology constitute the non-destructive physical measurement and defect detection disciplines that govern yield control across…
semiconductor mathematics, lithography mathematics, computational physics, numerical methods
Advanced Mathematics in Semiconductor Manufacturing 1. Lithography & Optical Physics This is arguably the most mathematically demanding area of semiconductor manufacturing. 1.1…
3d integration, chiplet, chiplets, cowos, hybrid bonding, microbump, tsv, hbm, hbm3e, hbm4, interposer, rdl, tcb, besi, disco, ucie, 2.5d packaging, heterogeneous integration, book 5
Advanced Packaging & 3D Integration: Beyond Moore's Law When the economic and physical scaling of photolithography hit the reticle-size limit ( ), the semiconductor industry…
chiplet heterogeneous integration, 2.5D interposer packaging, fan-out wafer level packaging, cowos
Interposers are the substrates that carry 2.5D integration: a die-to-die wiring layer dense enough to route thousands of connections between chiplets that sit side by side.…
advanced packaging and chiplet economics, advanced packaging chiplet, packaging chiplet economics, advanced packaging, packaging chiplet, chiplet economics
Advanced Packaging and Chiplet Economics Introduction & Motivation Advanced Packaging and Chiplet Economics addresses a central problem in manufacturing process control…
cowos info package platforms, 2.5d 3d hbm stacking, ucie die interconnect standard, hybrid bonding package substrate, cowos
Interposers are the substrates that carry 2.5D integration: a die-to-die wiring layer dense enough to route thousands of connections between chiplets that sit side by side.…
chip on wafer on substrate, hbm integration cowos, tsmc cowos s l r, silicon interposer packaging
Interposers are the substrates that carry 2.5D integration: a die-to-die wiring layer dense enough to route thousands of connections between chiplets that sit side by side.…
heterogeneous integration methods, chiplets
Advanced packaging is the set of technologies that connect, protect and cool silicon after it leaves the fab. It has moved from a cost-driven back-end afterthought to a primary…
fcbga, flip chip bga, abf substrate, coreless substrate, organic interposer packaging
Advanced Packaging Substrates are the organic multilayer circuit boards that mechanically support and electrically connect packaged ICs to printed circuit boards — serving as…
advanced packaging yield reliability prediction machine learning, advanced packaging, yield reliability prediction, csam, advanced packaging yield, packaging yield
Advanced Packaging Yield and Reliability Prediction with Machine Learning Introduction & Motivation Advanced Packaging Yield and Reliability Prediction with Machine Learning…
apc semiconductor, run to run control, feedback feedforward process, fab automation control
Advanced Process Control (APC) is the automated feedback and feedforward control system that adjusts process tool recipes in real time based on metrology measurements…
apc semiconductor, run to run control, feedback feedforward process, fab automation control, r2r control, ewma controller, ewma run to run control, metrology delay, apc framework, run to run control tuning, semi e133
Advanced process control is the layer of a fab that chooses what recipe the next lot will run, using what the last lot measured. It is not statistical process control, which…
source mask optimization, smo lithography, full chip smo, inverse lithography technology, opc
Computational Lithography and Optical Proximity Correction constitute the mathematical and algorithmic backbone of sub-wavelength semiconductor patterning. Operating deep within…
semiconductor packaging advanced, fan out wafer level, chiplet packaging
For most of computing history, more performance meant more transistors on one monolithic die. As that path slows, the industry increasingly gains performance through advanced…
advanced packaging predicting layer-to-layer registration accuracy in multilayer substrates using process parameters, advanced packaging predicting, packaging predicting layer-to-layer
Advanced Packaging: Predicting layer-to-layer registration accuracy in multilayer substrates using process parameters Introduction & Motivation Advanced Packaging: Predicting…
organic substrate scaling, glass core substrate, high density redistribution, substrate signal integrity, power delivery network, AI accelerator packaging, fine pitch routing, redistribution layer, substrate warpage
Advanced substrate technology is the next generation of package substrate platforms — built with finer routing lines and improved dielectric materials — that increase signal…
advanced mathematics, semiconductor mathematics, lithography math, plasma physics, diffusion math
Semiconductor Manufacturing: Advanced Mathematics 1. Lithography & Optical Physics This is arguably the most mathematically demanding area of semiconductor manufacturing. 1.1…
lithography
Aerial Image Inspection is a mask inspection technique that evaluates the mask based on the image it will actually produce in the lithographic exposure system — rather than…
defense, semiconductor, avionics, military, specification, mil, reliability
Aerospace Defense Semiconductor is military-grade semiconductor components for aircraft, missiles, defense systems meeting strict specifications for reliability, radiation…
afm profilometry, atomic force microscopy, atomic force microscope, afm metrology, metrology
Atomic force microscopy profiles a surface by rastering a sharp tip on a flexible cantilever and using a feedback-controlled z scanner to follow the tip-sample interaction.…
atomic force profilometry, contact mode afm, tapping mode afm, cd-afm, kelvin probe force microscopy, scanning capacitance microscopy, scm semiconductor
Atomic force microscopy profiles a surface by rastering a sharp tip on a flexible cantilever and using a feedback-controlled z scanner to follow the tip-sample interaction.…
metrology predicting afm calibration drift in surface roughness measurements, metrology predicting afm, predicting afm calibration, afm calibration drift, calibration drift surface
Metrology: Predicting AFM calibration drift in surface roughness measurements Introduction & Motivation Metrology: Predicting AFM calibration drift in surface roughness…
AI chip designs, high-throughput PPA, tensor cores, dataflow pipelines, systolic execution, systolic array, AI accelerator design, accelerator architecture, PPA optimization, power performance area
AI Chip Design: High-Throughput PPA for Tensor Workloads AI chip design is the practice of building silicon whose datapath, memory, and control logic are shaped around dense…
AI chip processing, process integration, semiconductor process integration, advanced node process, GAAFET process, FEOL process, BEOL process, nanosheet process, BSPDN process
AI Chip Process: Sub-2nm Gate-All-Around (GAA), Atomic Layer Processing, and Manufacturing Physics An AI chip process is the physical and chemical sequence that turns raw…
chip productivity, design productivity gap, EDA productivity, fab productivity, overall equipment effectiveness, OEE, predictive maintenance, FDC, MES dispatching, Kingman equation
AI Chip Productivity: Design Closure, Fab Throughput, OEE, and AI-Driven MES Optimization AI chip productivity measures the rate at which verified silicon design work and physical…
Wafer Defect, inspection, machine learning
AI-Driven Wafer Defect Inspection is an advanced quality control methodology employing artificial intelligence and deep learning algorithms to automatically detect, classify…