Bicmos Logic 1980s Find the Capacitive Load Crossover Point

# BiCMOS Logic (Late 1980s): Step 10 — Find the Capacitive-Load Crossover Point Where BiCMOS Wins

## 1. BiCMOS Has Its Own Fixed Overhead

Steps 8 and 9 showed BiCMOS winning at the loads tested, but the bipolar output stage is not advantage without cost even at the circuit level: the base-drive stage, the bipolar device's own junction capacitances, and its minimum turn-on delay add a fixed overhead to every transition, present whether the external load is large or vanishingly small. Pure CMOS, by contrast, has no such fixed-overhead stage — its delay scales from zero load upward with no equivalent floor.

## 2. Plotting Delay Against Load for Both Topologies

Plotting $t_{pd}$ against $C_L$ for both topologies on the same axes produces two curves: pure CMOS starting near zero delay at near-zero load and rising with a steeper slope as $C_L$ grows (per Step 8's $R_{on}C_L$ relationship), and BiCMOS starting at a nonzero delay floor set by its own fixed overhead but rising with a much shallower slope. The two curves cross at a specific load capacitance — commonly in the range of several picofarads to a few tens of picofarads on processes of this era, depending on the exact bipolar device's base-drive overhead — below which pure CMOS is faster, and above which BiCMOS is faster. This crossover point, not an unconditional ranking, is the correct way to decide which output topology a given node should use.

## 3. Companion Diagram One: Quantitative View

The Crossover: Fixed Overhead vs Scaling Slope t_pd against load capacitance, both topologies on one axis pure CMOS — low floor, steep slope BiCMOS — higher floor, shallow slope the exact load where the ranking flips wins below the crossover load wins above the crossover load the crossover point is a design input, not a fixed constant below it, pay no bipolar overhead; above it, the overhead is worth it

## 4. Companion Diagram Two: Structural View

Two Delay Budgets, Added Differently where each topology's total delay actually comes from PURE CMOS DELAY all of it scales with C_L, none of it is fixed BiCMOS FIXED PART base-drive + junction overhead, present at any load BiCMOS SCALING PART shallow C_L-dependent term, added on top the crossover is where BiCMOS's lower slope overtakes its higher floor

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