contact silicidation
**Contact Silicidation (Salicide Process)** is the **self-aligned formation of metal silicide at the source, drain, and gate poly surfaces by depositing a transition metal and annealing to react it with the underlying silicon, creating a low-resistivity metallic compound that dramatically reduces contact resistance between silicon and metal contacts** — a foundational CMOS process step that reduces the silicon sheet resistance by 10–50× and enables metal contacts to make efficient electrical connection to source/drain junctions. The "salicide" (self-aligned silicide) process defines itself — silicide forms only where metal contacts bare silicon, not where oxide or nitride spacers block the reaction.
**Salicide Process Flow**
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1. Pre-clean: Remove native oxide from S/D and gate surfaces (dilute HF)
2. Metal deposition: Sputter NiPt (5–10 nm) or Co (10–15 nm) over full wafer
3. First RTP anneal: 250–350°C (Ni) or 450–500°C (Co) → metal reacts with Si
→ Forms Ni₂Si (Ni) or CoSi (Co) — high-resistivity phase
4. Wet strip: Piranha (H₂SO₄:H₂O₂) removes unreacted metal over oxide/nitride spacers
(Silicide on Si/poly survives — unreacted metal on oxide dissolves)
5. Second RTP anneal: 400–500°C (Ni) or 700–850°C (Co) → converts to
→ NiSi (low ρ ~15 µΩ·cm) or CoSi₂ (low ρ ~15–20 µΩ·cm)
```
**Metal Silicide Comparison**
| Silicide | ρ (µΩ·cm) | Formation T | Thermal Stability | Key Issue |
|---------|----------|-----------|-----------------|----------|
| TiSi₂ | 15–20 | 700°C | Good | C54 formation challenge at <100nm |
| CoSi₂ | 15–20 | 750°C | Good | Co agglomeration at narrow lines |
| NiSi | 10–20 | 400°C | Fair (<500°C) | NiSi₂ spikes at high T |
| NiPtSi | 12–18 | 350°C | Better than NiSi | Pt slows agglomeration |
| PtSi | 35–45 | 300°C | Good | High ρ — only for IR detectors |
**NiPt Silicide (NiPtSi) — Advanced Node Standard**
- Ni alloyed with 5–10% Pt → lower formation temperature → less dopant diffusion during anneal.
- Pt substitutes for Ni in NiPt lattice → retards agglomeration of NiSi at elevated temperatures → improves thermal stability.
- Pt also improves junction leakage (NiPtSi has fewer spikes into junctions).
- Industry standard from 65nm through 14nm FinFET nodes.
**Contact Resistance Components**
- Total contact resistance (Rc) = metal/silicide interface resistance + silicide/Si interface (ρc, specific contact resistivity).
- ρc (Ω·cm²) for NiPtSi/n-Si: ~2–5 × 10⁻⁸ Ω·cm² (heavily doped, >10²⁰ cm⁻³).
- At narrow contact areas (5nm × 5nm): Rc = ρc / A → Rc = (3×10⁻⁸) / (25×10⁻¹⁴) = 12,000 Ω → severe problem.
- **Solution at 5nm**: Replace NiPt with Ti or TiSiN contacts → lower ρc through metal-semiconductor interface engineering.
**Silicide at FinFET Nodes**
- FinFET S/D area is very small (fin width × fin height for each fin) → small silicide area → higher contact resistance.
- Multi-fin transistors: Silicide must cover all fin surfaces conformally.
- NiPt deposition into confined S/D — conformality of sputtered NiPt limits coverage on fin sidewalls.
- Alternative: Ti + ALD TiN liner → forms TiSi₂ or Ti₅Si₃ with better conformality.
**Gate Poly Silicidation**
- In poly-gate CMOS (pre-HKMG): Gate poly also silicided to reduce gate resistance.
- In HKMG (gate-last): No silicide on metal gate (already low-resistance metal) → salicide only on S/D.
- SAB (salicide block) mask defines which regions receive silicide vs. remain blocked.
Contact silicidation is **the chemical metallurgy step that makes silicon-to-metal contacts electrically practical** — by transforming high-resistance silicon surfaces into metallic silicide with sheet resistance of 3–8 Ω/□, the salicide process enables the low-resistance source/drain contacts that allow transistors to deliver their full drive current into circuit loads, remaining one of the most impactful yet least-noticed steps in the entire CMOS process flow.