embedded sige source/drain

**Embedded SiGe Source/Drain (eSiGe S/D)** is a **strain engineering technique for PMOS transistors** — where the source and drain regions are etched and refilled with epitaxially grown Silicon-Germanium, which has a larger lattice constant than Si, inducing uniaxial compressive stress in the channel. **How Does eSiGe Work?** - **Process**: 1. Etch cavities in the source/drain regions (Sigma-shaped or diamond-shaped recess). 2. Epitaxially grow $Si_{1-x}Ge_x$ ($x$ = 20-40% Ge content) in the cavities. 3. The larger SiGe lattice pushes against the channel from both sides -> compressive strain. - **Enhancement**: Higher Ge content = more strain = more mobility boost (limited by defect formation). **Why It Matters** - **PMOS Game-Changer**: Provides 30-50% hole mobility improvement. Pioneered by Intel at 90nm (2003). - **Uniaxial Stress**: More effective than biaxial global strain because uniaxial stress is maintained at short channel lengths. - **Standard Process**: Used by every major foundry from 90nm through FinFET nodes. **Embedded SiGe S/D** is **squeezing the channel for speed** — using the larger SiGe crystal to compress the silicon channel and dramatically boost PMOS performance.