fan-out wafer-level packaging

```svg Fan-out wafer-level packaging: no substrate, RDL straight on the dieDies re-molded into a wafer; copper RDL fans I/O out past the die edge — thinner and cheaper than a package substrate1 · The fan-out structurediemoldmoldRDL — Cu in polymerfan-outfan-outA die is re-molded into a wafer.Copper RDL is built on its face andfans I/O out past the die edge.No package substrate at all —RDL replaces it entirely.Package height can drop below0.5 mm — great for mobile SoCs.2 · Chip-first vs chip-lastChip-first (RDL last)1234Place dies on a carrierMold — reconstituted waferDebond the carrierBuild RDL on die face + ballsSimple RDL — but dies shift in the moldChip-last (RDL first)1234Build RDL on a carrier firstAttach known-good diesMold, then debondDrop balls + singulateRDL proven first — less die-shiftBoth skip the substrate; order tradesyield against process steps.3 · Why it wins & hard partsWhy it winsNo substrate → package < 0.5 mmCheaper — ~50–70% vs substrateShort RDL → better electricalDie near board → better thermalScales: InFO-PoP, InFO-LThe hard partsdie-shift & placement accuracyreconstituted-wafer warpageRDL yield over a large areathermal for high-power devicesWarpage and die movement in themold are the yield gate.No substrate, RDL on the dieCopper redistribution is built straightonto the molded die face; the organicpackage substrate disappears.Fan-out adds I/O roomRouting past the die edge gives moreballs at board-friendly pitch thanfan-in WLCSP can.Warpage & die-shift biteReconstituted-wafer warpage and diemovement in the mold gate FOWLPyield. ``` Fan-Out Wafer-Level Packaging (FOWLP) packages dies at wafer scale with redistribution layers extending beyond the die area, eliminating traditional substrates and enabling thin, cost-effective packages with excellent electrical performance. The process embeds dies face-up in molding compound on a carrier wafer, creating a reconstituted wafer. RDL is then fabricated over the entire wafer surface, routing connections from die pads to solder balls in the fan-out area. After RDL completion, the carrier is removed and individual packages are singulated. FOWLP provides several advantages: thinner packages (0.5-1mm) than traditional packaging, lower cost by eliminating substrates, better electrical performance from short interconnects, and scalability to large die sizes. The fan-out area accommodates more I/Os at relaxed pitch for board assembly. FOWLP is widely used for mobile processors, RF modules, and power management ICs. Variations include fan-out panel-level packaging (FOPLP) for higher throughput and embedded multi-die interconnect bridge (EMIB) for chiplet integration. Challenges include warpage management, RDL yield, and thermal performance for high-power devices.

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