Microprocessor 1971 Step 18 Name the Memory Thread DRAM Hmos Handoff

# Name the Memory Thread This Series Leaned On Without Retelling It

## 1. Step 6's Program ROM Assumed a Memory Technology This Series Never Built

Step 6 of this series describes storing the program in a separate read-only memory chip, and Step 3's bus multiplexing exists specifically because address and data had to travel between the processor and that memory chip, and the companion RAM chip, over a pin-limited package. Neither step builds the memory devices themselves from first principles — they treat "a ROM chip" and "a RAM chip" as available building blocks, the same way this series treats silicon-gate PMOS fabrication in Step 4 as an available process rather than something this series derives.

The memory side of that relationship belongs to a different thread in this project's own history, one that was already running in parallel with the 4004's own design and that continued independently afterward. `dram_1968`, `dramscaling_1974`, and `dram64k_1979` (named here only, not retold — those series' own device physics and cell-scaling story stand on their own) cover the dynamic memory technology whose density curve eventually let later systems hold far more program and working memory than the 4004's own 4001 and 4002 companion chips offered. This series does not depend on any content from those series technically, but the pin-count and bus-multiplexing pressure Step 3 and Step 7 describe is the processor-side mirror of exactly the storage-density problem that memory thread was independently solving.

Two Parallel Threads, Meeting at the Memory Bus this series built the processor side; a separate thread built the memory side THIS SERIES processor reads stored instructions treats ROM/RAM chips as given (Step 6) bus multiplexing (Step 3) exists because of pin limits on those chips PARALLEL MEMORY THREAD dram_1968, dramscaling_1974, dram64k_1979 named only — own device physics, not retold here density growth that later relaxed the pin-count pressure this series' Step 3 faced bus demand density supply

## 2. Why Step 7's Clock Multiplexing Would Have Mattered Less if Memory Had Been Different

Step 7 confronts the need for multi-phase clocking as a direct consequence of sharing one physical bus between address and data across a pin-limited package. That pin limit exists because the 4004's own companion memory chips, built on technology contemporaneous with the processor itself, had not yet reached the densities later memory technology would achieve — if the program and data memory this series' processor talked to had offered much higher density per pin from the start, the multiplexing pressure driving Step 3's and Step 7's design decisions would have been correspondingly lighter. This is not a claim that the 4004's designers were working around DRAM's own limitations directly — the 4001 and 4002 companion chips are not DRAM — but the general historical pressure toward higher memory density per package pin was one problem across the industry at that time, and this series' architecture reflects the processor side of living with that pressure's early-1970s severity.

`hmos_1978` (named here only) later addressed a related but distinct pressure — process-level speed and density improvements applied to microprocessors and their memory specifically, roughly seven years after the 4004 — and this series does not retell that account either; it is named solely to mark where, chronologically, the next systematic improvement to the processor-memory relationship this series describes occurs.

A Chronology of Pressure on the Processor-Memory Relationship each point named only where this series' own content ends 4004 released1971, this series dram64k_1979 era density gainsnamed only hmos_1978named only NO CONTENT FROM EITHER THREAD IS RETOLD HERE this step only marks where this series' own bus-multiplexing account sits relative to a parallel, independently told memory-technology story

## 3. Why This Step Does Not Create a Forced Handoff

This step does not claim this series hands off to the DRAM or HMOS threads, or that either of those threads depends on this series. It establishes something narrower and more honest: Steps 3, 6, and 7 of this series assumed memory building blocks whose own improvement over time belongs to a different, independently documented story, and naming that story by its actual series names, without retelling its content, is more accurate than either ignoring the dependency or manufacturing a connection this series' own architecture does not actually require.

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