nanosheet stacking

**Nanosheet Stacking** is the **process of building multi-layer Si/SiGe superlattice stacks that form the channels of Gate-All-Around (GAA) transistors** — the number, thickness, spacing, and quality of stacked nanosheets directly determine device performance. **Stacking Process** - **Epitaxy**: Grow alternating Si/SiGe layers by epitaxy (typically 3-5 Si channels with SiGe sacrificial layers). - **Patterning**: Etch the superlattice stack into fins. - **Release**: Selectively etch SiGe sacrificial layers to release freestanding Si nanosheets. - **Gate Wrap**: Deposit gate stack that wraps completely around each released nanosheet. **Why It Matters** - **Current Drive**: More nanosheets = more effective channel width = higher drive current per footprint. - **Sheet Thickness**: Thinner sheets improve gate control (less SCE) but reduce current per sheet. - **Spacing**: Tighter vertical spacing increases density but makes gate fill more challenging. **Nanosheet Stacking** is **building the transistor layer cake** — growing and releasing multiple channel layers for the gate to wrap around in GAA devices.