Sf1-4-Process
SF1.4 is Samsung Foundry’s name for its planned 1.4nm-class logic manufacturing generation, extending the company’s gate-all-around development direction. Samsung’s fourth-quarter 2025 earnings-call transcript, delivered in January 2026, sets a 2029 mass-production goal. This makes SF1.4 a developing process platform rather than an available chip product. Its name identifies a technology generation; it does not specify a 1.4nm physical gate length or directly establish transistor density, clock speed or energy efficiency.
The roadmap has a publication date. Samsung’s June 2024 Foundry Forum release still targeted SF1.4 production in 2027. Its later fourth-quarter 2025 earnings-call transcript instead describes development toward 2029 and plans for PDK version 1.0 in the second half of the following year, meaning 2027. These are stated goals for process development and customer enablement. They establish the planning sequence, while a production release, qualified customer design and sustained manufacturing ramp remain separate milestones. [Samsung earnings-call transcript](https://irsvc.teletogether.com/sec/pdf/2025Q4_script_eng.pdf?1=).
Gate control is the transistor foundation. Samsung’s MBCFET technology uses stacked nanosheet channels with the gate surrounding the channel cross-section. Its published explanation describes channel-width adjustment as a way to balance drive capability and power for different designs. In general, stronger electrostatic control helps manage the behavior of very small transistors, while contact resistance, capacitance and leakage still matter. The physical stack below illustrates this GAA development context; its dimensions, sheet count, gate materials and wiring layers are not disclosed SF1.4 specifications.
Useful density depends on the whole layout. A logic cell must accommodate transistors, isolation, contacts, supply connections and enough routing access to connect neighboring cells. A smaller nominal node therefore does not translate directly into an equivalent reduction in die area. SRAM, analog blocks and interface circuits can scale differently from dense logic. Designers evaluate cell libraries, memory macros and a routed block under the applicable design rules. The resulting functional density matters more than a numerical comparison between two foundries’ process names.
Interconnect and variation set practical limits. A faster device helps only if its contacts and wires can deliver a signal within the timing budget. Wire resistance, capacitance, coupling and supply voltage drop can consume that improvement. At the same time, small pattern shifts or changes in feature size affect electrical behavior and manufacturing margin. The compact plan view shows why reducing a metal landing area leaves less room for via misalignment. It is a general illustration of process control, rather than an SF1.4 minimum-width or overlay specification.
Lithography is a qualified layer-by-layer choice. ASML explains that numerical aperture and wavelength influence optical resolution; its High-NA EUV platform raises numerical aperture from 0.33 to 0.55. A scanner capability alone does not identify the exposure strategy of an entire foundry process. Resist behavior, masks, etching, overlay control and defect inspection must also work together. The SF1.4 process name does not establish a particular High-NA insertion plan. Likewise, Samsung’s SF2Z backside-power announcement should retain its own node label rather than being treated as an automatic SF1.4 feature.
A complete process includes its design ecosystem and manufacturing evidence. A production program needs usable transistor models, extraction rules, characterized cells, verified memory and interface IP, reliability limits and silicon measurements. Designers then close timing, power and signal integrity across the required operating conditions before qualifying the product and package. SF1.4’s value will ultimately be demonstrated by reproducible circuit results, good-die yield, delivered volume and cost per working product. A roadmap target or nominal node number supplies only part of that evidence.
Sources and further reading. [Samsung’s fourth-quarter 2025 earnings-call transcript: 2029 target and PDK plans](https://irsvc.teletogether.com/sec/pdf/2025Q4_script_eng.pdf?1=); [Samsung Foundry Forum 2024: historical SF1.4 plan and separate SF2Z disclosure](https://semiconductor.samsung.com/news-events/news/samsung-showcases-ai-era-vision-and-latest-foundry-technologies-at-sff-2024/); [Samsung’s MBCFET device explanation](https://semiconductor.samsung.com/news-events/tech-blog/samsung-opens-the-gate-to-transistor-performance-power-and-area-improvements-with-mbcfet/); [ASML’s EUV systems and numerical aperture](https://www.asml.com/en/products/euv-lithography-systems).
Read SF1.4 as a developing manufacturing platform: connect the dated roadmap to qualified devices, design rules, routed circuits and demonstrated production results.