wafer level burn in
**Wafer-Level Burn-In (WLBI) and Known Good Die (KGD) Testing** is the **semiconductor test methodology that applies electrical stress and elevated temperature to dies while still on the wafer** — screening out early-life failures (infant mortality) before packaging, which is critical for advanced packaging technologies like chiplets, 2.5D/3D integration, and HBM stacking where a single defective die in a multi-die assembly would waste all other good dies and the expensive packaging.
**Why WLBI Matters**
```
Traditional flow: Advanced packaging flow:
[Wafer test] → [Package] → [Burn-in] → [Ship] Problem: Packaged bad die!
90% yield $0.10/die Find fails But waste packaging cost
With WLBI: Solution: Test BEFORE packaging!
[Wafer test] → [WLBI at wafer] → [KGD only] → [Package] → [Ship]
90% yield Screen infant Only known good dies enter packaging
mortality → No wasted packaging
```
**Economic Justification**
| Scenario | Without KGD | With KGD/WLBI |
|----------|------------|---------------|
| Die yield | 90% | 90% |
| Die cost | $50 | $50 + $5 (WLBI) |
| Package cost (chiplet) | $200 | $200 |
| Assembly yield (4-die) | 0.9⁴ = 65.6% | ~95% (KGD vetted) |
| Effective cost per good module | $760 | $440 |
| Savings | — | 42% |
- For a 4-chiplet module at 90% die yield, WLBI saves 42% overall cost.
- For HBM (8-die stack at 95% per die): Without KGD: 0.95⁸ = 66% yield. With KGD: ~95%.
**WLBI Process**
```
[Wafer from fab]
↓
[Wafer probe with temporary contacts (MEMS probes or elastomer)]
↓
[Apply Vdd + stress voltage at elevated temperature (85-125°C)]
[Duration: 1-48 hours]
↓
[Re-test: Identify dies that degraded or failed during burn-in]
↓
[Ink/map failed dies → only ship Known Good Die]
```
**WLBI Equipment Challenges**
| Challenge | Issue | Solution |
|-----------|-------|----------|
| Contact resistance | Must contact every die pad simultaneously | Advanced probe cards (MEMS, cantilever) |
| Temperature uniformity | Heat 300mm wafer uniformly to 125°C | Thermal chuck with multi-zone control |
| Parallelism | Test all dies simultaneously | Massively parallel DFT + scan |
| Probe damage | Repeated contact damages bond pads | Cu pillar probe areas, sacrificial pads |
| Alignment | Align probes to millions of pads | <1 µm alignment accuracy needed |
**Known Good Die (KGD) Quality Levels**
| Level | Test Content | DPPM Target | Application |
|-------|-------------|------------|-------------|
| KGD Level 0 | Wafer probe only | ~1000 DPPM | Consumer |
| KGD Level 1 | Probe + full at-speed test | ~100 DPPM | Automotive, server |
| KGD Level 2 | Probe + WLBI + retest | ~10 DPPM | HBM, chiplet, 3D |
| KGD Level 3 | Probe + WLBI + multiple retests | <1 DPPM | Safety-critical |
**HBM and Chiplet Drivers**
- HBM3: 8-12 die stack, bonded permanently → one bad die = entire stack scrapped.
- Advanced chiplets (Intel Ponte Vecchio, AMD MI300): 4-8+ dies per module.
- TSMC CoWoS: 2.5D with $1000+ interposer → cannot afford bad die.
- Industry consensus: WLBI is mandatory for all multi-die integration going forward.
Wafer-level burn-in and KGD testing are **the quality assurance gates that make multi-die semiconductor products economically viable** — by screening out infant mortality failures before committing to expensive advanced packaging assembly, WLBI ensures that only verified good dies enter the packaging process, transforming the economics of chiplets and 3D integration from yield-limited to practical high-volume manufacturing.