27,049 technical terms and definitions
ai accelerator chip explained, ai accelerator vs gpu, ai accelerator meaning, types of ai accelerators
An AI accelerator is any chip built specifically to speed up the math behind artificial intelligence — mostly large-scale matrix multiplication — rather than to handle…
An alignment mark is a small reference fiducial pattern etched onto a wafer during an early process step, used by a lithography scanner to precisely position each subsequent…
integrated device manufacturer meaning, idm vs fabless, idm semiconductor company, what does idm mean in chips
An IDM, or Integrated Device Manufacturer, is a chip company that both designs its chips and manufactures them in its own fabrication plants — the opposite of the fabless model…
An interposer is an intermediate layer placed between one or more chip dies and the package substrate, providing dense, short interconnects that let multiple separate dies…
npu explained, neural processing unit, npu vs gpu vs cpu, on-device ai chip
An NPU, or Neural Processing Unit, is a chip or chip block built specifically to run the repetitive math behind neural networks — mostly large batches of matrix multiplication…
osat semiconductor meaning, outsourced assembly and test explained, osat vs foundry, chip packaging and testing company
An OSAT — short for Outsourced Semiconductor Assembly and Test — is a company that specializes in packaging finished silicon dies and testing completed chips, handling…
Atomic layer deposition, or ALD, is a thin-film deposition technique that builds up material one atomic layer at a time through a sequence of self-limiting chemical reactions…
transformer attention explained, query key value attention, kv cache explained, multi query attention, grouped query attention, self attention transformer
The attention mechanism is the calculation that lets a transformer decide, for every token it's producing, which earlier tokens actually matter right now — and it's exactly what…
what is BEOL
Back-end-of-line, or BEOL, refers to the later stage of chip fabrication where the metal wiring layers connecting all the transistors together are built up on top of the wafer…
Backside power delivery is a chip design approach that moves the power distribution network from the front side of the wafer, where signal wiring lives, to the back side, freeing…
beamforming explained, beamforming 5g meaning, how does beamforming work, beamforming antenna array
Beamforming is a wireless antenna technique that combines signals from multiple antenna elements so they reinforce each other in a specific direction, effectively focusing…
Branch prediction is a processor technique that guesses which way a program's conditional branch will go before that branch is actually evaluated, letting the processor keep…
what is burn in testing
Burn-in testing is a reliability screening step where chips are operated under elevated temperature and voltage stress for an extended period before shipment, deliberately…
Cache coherence is the property that guarantees every processor core in a multi-core chip sees a consistent, up-to-date view of shared memory, even though each core keeps its own…
A cache hierarchy is a layered arrangement of multiple cache memory levels between a processor and main memory, each successive level trading some speed for greater capacity…
Carrier aggregation is a wireless technology that combines multiple separate frequency bands, or carriers, into one effective connection, letting a device use more total bandwidth…
Chemical mechanical polishing, or CMP, is a process that combines a chemical slurry with mechanical grinding to precisely flatten a wafer's surface between processing steps…
Chemical vapor deposition, or CVD, is a thin-film deposition technique where gaseous chemical precursors react at a wafer's surface to form a solid material layer, offering faster…
chip packaging explained, semiconductor packaging meaning, advanced packaging chiplets, what is a chip package
Chip packaging is the process of taking a finished, tested silicon die and encasing it in a protective housing with external connectors — the familiar black rectangle with metal…
Clock domain crossing is the transfer of a signal from a circuit block running on one clock to a circuit block running on a different, asynchronous clock, a situation that…
clock speed explained, cpu ghz meaning, what is clock frequency, clock speed vs performance
Clock speed, measured in gigahertz (GHz), is how many times per second a chip's internal clock ticks, and each tick synchronizes one step of work across the chip's circuits — but…
chemical mechanical polishing explained, planarization semiconductor, cmp dishing erosion, copper damascene cmp, preston equation polishing
Chemical-Mechanical Polishing (CMP) is what flattens the wafer back out after deposition and etch leave it bumpy. Every layer built through the CVD-lithography-etch loop leaves…
compute in memory explained, in memory computing ai, compute in memory chip meaning, what does compute in memory mean
Compute-in-memory is a chip architecture approach that performs certain calculations directly inside memory itself, rather than following the traditional design of moving data out…
Contact resistance is the electrical resistance that occurs specifically at the interface between two different materials, such as a metal contact and a transistor's source…
dynamic batching llm serving, in-flight batching explained, llm throughput scheduling, static vs continuous batching, ai serving scheduler
Continuous batching is the serving-system technique that decides which requests actually get processed together on any given decode step, and it's the layer where every…
damascene process explained, dual damascene semiconductor, copper electroplating BEOL, barrier metal liner copper, low-k dielectric interconnect
Copper interconnect is the wiring that connects millions or billions of individual transistors into an actual working circuit. Once the transistors themselves are built through…
cpu cache explained, l1 l2 l3 cache, how does cache memory work, cache hit miss
CPU cache is a small amount of extremely fast memory built directly into the processor to hide an enormous speed gap: a modern CPU can perform an operation in a fraction of…
critical dimension explained, cd semiconductor meaning, critical dimension lithography, what does cd mean in chip manufacturing
Critical dimension, often abbreviated CD, refers to the smallest, most precisely controlled feature size on a chip — typically the width of the narrowest transistor gate or wire…
cryogenic plasma etch explained, high aspect ratio sidewall control, low temperature etch semiconductor, tsv etch profile, gaa release etch sidewall bowing
Cryo etch is plasma etching performed with the wafer cooled to extremely low temperatures, and it exists to solve an etch-profile problem that ordinary room-temperature…
chemical vapor deposition explained, CVD vs ALD semiconductor, PECVD LPCVD thermal CVD, step coverage conformality, thin film deposition chip fabrication
Chemical Vapor Deposition (CVD) is how a fab builds material up on the wafer instead of carving it away. Where plasma etch removes everything outside the mask, CVD does…
Defect density is a measure of how many manufacturing defects occur per unit area of a wafer, used as a key indicator of a fabrication process's health and a critical input…
dof lithography explained, depth of focus meaning chip, lithography focus tolerance, dof semiconductor
Depth of focus, or DOF, is the vertical range above and below a lithography system's ideal focal plane within which a pattern can still be exposed sharply enough to be usable…
Die attach is the packaging step that permanently bonds a chip's silicon die to its package substrate or lead frame, providing both the mechanical foundation that holds the chip…
all reduce explained, ring allreduce vs tree allreduce, gradient synchronization gpu cluster, collective communication ai training, training cluster interconnect bandwidth
Distributed training is how a single model gets trained across thousands of chips at once, and the mechanism that makes it work — collective communication, most commonly…
Dual damascene is an interconnect fabrication technique that etches both a via hole and its overlying metal trench into the insulating layer before a single metal fill, forming…
deep ultraviolet lithography explained, duv vs euv, duv lithography meaning, 193nm lithography
DUV, or deep ultraviolet lithography, is the workhorse lithography technology that patterned chips for decades before EUV arrived, using a longer wavelength of ultraviolet light…
edge ai explained, edge ai vs cloud ai, on-device ai meaning, what does edge ai mean
Edge AI means running artificial intelligence directly on the device where data is generated — a phone, a camera, a car, a factory sensor — instead of sending that data to…
Edge placement error, or EPE, is the total deviation between where a feature's edge is actually formed on a chip and where it was intended to be, combining both lithography…
euv lithography explained, extreme ultraviolet lithography meaning, how does euv work, euv chip manufacturing
EUV lithography is a chipmaking technique that uses extreme ultraviolet light — with a wavelength roughly fourteen times shorter than the light used in older lithography methods…
fabless company meaning, fabless vs idm, fabless semiconductor model, what does fabless mean
A fabless company designs chips but doesn't own or operate the factories that manufacture them, instead paying a foundry to fabricate its designs — a business model that lets…
Fan-out wafer-level packaging, or FOWLP, is a chip packaging method that embeds individual dies in a reconstituted mold compound and builds redistribution wiring extending beyond…
federated learning explained, federated ai training meaning, federated learning privacy, what does federated learning do
Federated learning is a way of training AI models across many separate devices or locations without ever centralizing the underlying data — each device trains on its own local…
Fine-tuning is the process of taking an already-trained general-purpose model and further training it on a smaller, more specific dataset, adapting its behavior for a particular…
what is a finfet, gate all around transistor explained, nanosheet transistor architecture, 3nm transistor structure, gate all around vs finfet
FinFET and GAA (Gate-All-Around) are the two transistor shapes the entire fab process you've just walked through was actually built to produce. Every step covered so far — litho…
flip chip explained, flip chip vs wire bonding, flip chip bonding meaning, what does flip chip mean
Flip chip packaging is a method of connecting a silicon die to its package by flipping the die upside down and attaching it directly via an array of tiny solder bumps across its…
what is FEOL
Front-end-of-line, or FEOL, refers to the earlier stage of chip fabrication where individual transistors are actually built into the silicon wafer itself, before any of the metal…
high k dielectric explained, gate leakage quantum tunneling, silicon dioxide gate insulator, transistor gate dielectric, gate oxide thickness scaling
Gate oxide is the thin insulating layer sitting directly between a transistor's gate and its channel, and its whole job is to let the gate control the channel electrically without…
multi query attention explained, gqa vs mqa, kv cache size reduction, attention heads sharing keys values, llm serving memory optimization
Multi-query and grouped-query attention are two ways of shrinking the KV cache itself, by making multiple attention heads share the same keys and values instead of each head…
Gradient checkpointing is a training technique that discards most intermediate activations during a neural network's forward pass and recomputes them as needed during the backward…
hbm explained, hbm meaning ai chips, high bandwidth memory vs regular memory, what does hbm stand for
High bandwidth memory, or HBM, is a type of memory built by stacking multiple memory dies vertically and connecting them with extremely short, wide internal connections, achieving…