29,006 technical terms and definitions
Chemical Thermodynamics, Phase Equilibria, and Electrochemical Potential 1. Thermodynamic descriptions of chemical systems Chemical thermodynamics connects measurable heat, work…
chemical usage prediction process control, chemical usage prediction, usage prediction process, prediction process control, chemical usage, usage prediction, process control
Chemical Usage Prediction Process Control with Machine Learning Introduction & Motivation Chemical Usage Prediction Process Control with Machine Learning addresses a central…
cvd process, lpcvd pecvd, cvd semiconductor, thin film cvd
Chemical vapor deposition grows a solid film out of gas: reactant precursor gases flow over a heated wafer, react at or near its surface, and leave behind a solid layer while…
pecvd lpcvd process, thin film deposition semiconductor, cvd precursor chemistry, plasma enhanced cvd
Chemical Vapor Deposition (CVD) is the thin-film deposition technique that grows solid films on a heated substrate by introducing gaseous precursors that chemically react on…
pecvd lpcvd, thin film deposition cvd, cvd precursor chemistry, conformal cvd film
Chemical Vapor Deposition (CVD) is the thin film deposition technique that grows solid films on wafer surfaces through chemical reactions of vapor-phase precursors — producing…
pecvd lpcvd mocvd, cvd thin film semiconductor, cvd precursor chemistry, dielectric cvd deposition
Chemical Vapor Deposition (CVD) is the thin film deposition technique that forms solid materials on a substrate through chemical reactions of gaseous precursors — producing…
chemical vapor, vapor deposition, 900k cvd ml rt t1 t2, chemical vapor deposition, vapor deposition optimization, deposition optimization
Chemical Vapor Deposition Optimization Introduction & Motivation Optimizing CVD processes through ML accelerates semiconductor and materials manufacturing. ML models predict…
pecvd lpcvd techniques, atomic layer deposition ald, cvd film conformality, deposition rate uniformity control
Chemical Vapor Deposition CVD Process Variants — Fundamental thin film deposition technologies that form dielectric, semiconductor, and metallic layers through gas-phase chemical…
chemical vapor deposition reactor temperature uniformity prediction, chemical vapor deposition, vapor deposition reactor, deposition reactor temperature
Chemical Vapor Deposition Reactor Temperature Uniformity Prediction with Machine Learning Introduction & Motivation Chemical Vapor Deposition Reactor Temperature Uniformity…
MOCVD, APCVD, SACVD, CVD comparison
Chemical Vapor Deposition (CVD) Variants span a family of thin-film deposition techniques — LPCVD, PECVD, APCVD, SACVD, MOCVD, and HDPCVD — each operating at different pressure…
environmental & sustainability
Chemical waste is waste streams containing hazardous or regulated chemical substances from manufacturing - Segregation, labeling, storage, and treatment protocols control risk…
chemical waste neutralization ph drift prediction machine learning, chemical waste, neutralization ph drift, chemical waste neutralization ph drift prediction
Chemical Waste Neutralization pH Drift Prediction with Machine Learning Introduction & Motivation Chemical Waste Neutralization pH Drift Prediction with Machine Learning addresses…
chemical waste treatment efficiency prediction, chemical waste treatment, waste treatment efficiency, treatment efficiency prediction, chemical waste, waste treatment
Chemical Waste Treatment Efficiency Prediction with Machine Learning Introduction & Motivation Chemical Waste Treatment Efficiency Prediction with Machine Learning addresses…
car, photoresist chemistry, euv resist, photoresist
Photoresist chemistry and track coat-bake-develop processing constitute the photochemical foundation of semiconductor patterning, converting aerial optical and extreme ultraviolet…
chemically amplified resist, car, lithography, photoresist chemistry
Photoresist chemistry and track coat-bake-develop processing constitute the photochemical foundation of semiconductor patterning, converting aerial optical and extreme ultraviolet…
chemically amplified resist sensitivity drift prediction, chemically amplified resist, amplified resist sensitivity, resist sensitivity drift, chemically amplified
Chemically Amplified Resist Sensitivity Drift Prediction with Machine Learning Introduction & Motivation Chemically Amplified Resist Sensitivity Drift Prediction with Machine…
chemistry ai
ChemNER is the fine-grained chemical named entity recognition benchmark and framework — extending standard chemical NER beyond compound detection to classify chemical entities…
chenming hu, what is chenming hu
Chenming Hu is a semiconductor-device researcher associated with MOSFET scaling, modeling, and FinFET development. His work is relevant here because the deep-submicron transition…
chi-squared, Pearson 1900, goodness-of-fit test, test of independence, degrees of freedom, contingency table, Fisher 1922
The chi-square distribution is the distribution of a sum of squared independent standard normal variables: if Z1 through Zk are independent standard normals, then Z1² + Z2² + ...…
quality & reliability
Chi-Square Test is a categorical-data test that compares observed counts to expected counts under a null model - It is a core method in modern semiconductor statistical…
microlens offset, image sensor, pixel shift, vignetting, light collection efficiency
Chief Ray Angle and Microlens Offset Compensation Light reaching a pixel near the edge of an image sensor arrives at a steep angle rather than straight down, because the camera…
chill plate thermal recovery prediction machine learning, chill plate, thermal recovery prediction, cd, chill plate thermal recovery prediction, chill plate thermal
Chill Plate Thermal Recovery Prediction with Machine Learning Introduction & Motivation Chill Plate Thermal Recovery Prediction with Machine Learning addresses a central problem…
chilled water loop temperature drift prediction machine learning, chilled water, loop temperature drift, chilled water loop temperature drift prediction, water loop
Chilled Water Loop Temperature Drift Prediction with Machine Learning Introduction & Motivation Chilled Water Loop Temperature Drift Prediction with Machine Learning addresses…
environmental & sustainability
Chilled Water Optimization is control tuning of chilled-water plants to minimize energy per unit of cooling delivered - It improves plant efficiency by coordinating chillers…
facility
Chilled water systems in semiconductor fabrication facilities provide centralized cooling to process tools, HVAC systems, and facility infrastructure through a closed-loop network…
manufacturing equipment
Chiller is refrigeration-based system that removes heat from process loops to maintain target temperatures - It is a core method in modern semiconductor AI, manufacturing control…
chiller coolant purity maintenance, chiller coolant purity, coolant purity maintenance, chiller coolant, coolant purity, purity maintenance
Chiller Coolant Purity Maintenance with Machine Learning Introduction & Motivation Chiller Coolant Purity Maintenance with Machine Learning addresses a central problem in process…
fab operations predicting coolant purity degradation for predictive maintenance scheduling, fab operations predicting, operations predicting coolant, predicting coolant purity
Fab Operations: Predicting coolant purity degradation for predictive maintenance scheduling Introduction & Motivation Fab Operations: Predicting coolant purity degradation…
chiller coolant purity maintenance, chiller coolant purity, coolant purity maintenance, chiller coolant, coolant purity, purity maintenance
Chiller Coolant Purity Maintenance with Machine Learning Introduction & Motivation Chiller Coolant Purity Maintenance with Machine Learning addresses a central problem in process…
china semiconductor development push, what is china semiconductor development push
China’s semiconductor development push describes a collection of industrial-policy and investment efforts. It is not one fabrication process, company, or completed capability.…
foundation model
A scaling law is an empirical power-law relationship describing how a language model's loss falls as model size, training data, or compute increases — smoothly and predictably…
scaling laws
A scaling law is an empirical power-law relationship describing how a language model's loss falls as model size, training data, or compute increases — smoothly and predictably…
model design
Scaling laws are the empirical power-law relationships that predict how a language model's loss falls as you add parameters, training data, and compute. They are the reason…
model training
A scaling law is an empirical power-law relationship describing how a language model's loss falls as model size, training data, or compute increases — smoothly and predictably…
scaling laws
A scaling law is an empirical power-law relationship describing how a language model's loss falls as model size, training data, or compute increases — smoothly and predictably…
training
A scaling law is an empirical power-law relationship describing how a language model's loss falls as model size, training data, or compute increases — smoothly and predictably…
中文, 翻译, english, 中英
Multilingual LLMs (中英双语) Models Optimized for Chinese Chinese-First Models Model Provider Parameters Highlights Qwen 2 Alibaba 7B-72B Best Chinese open model ChatGLM Zhipu AI…
Searle 1980, Minds Brains and Programs, syntax vs semantics, strong AI, systems reply, robot reply, symbol grounding problem
The Chinese room argument is a thought experiment published by the philosopher John Searle in 1980 to show that running a computer program is not sufficient for understanding.…
semiconductor chip, chip manufacturing, how to make a chip, semiconductor manufacturing, chip fabrication, wafer processing
Making a modern chip means building a three-dimensional structure of 60–100+ patterned layers onto a silicon wafer, one atomic-scale layer at a time. At a high level, the flow…
microarchitecture, memory hierarchy, cache coherence, interconnect fabric, network-on-chip, NoC, chiplet interconnect, MESI protocol, die-to-die interconnect
Chip Architecture: Microarchitecture, Memory Hierarchy, and Interconnect Fabric Chip architecture is the set of structural decisions — how compute units are organized, how memory…
what is chip binning, cpu binning explained, why are some chips faster, binning semiconductor, silicon lottery
Chip binning is why two processors that came off the exact same design and the exact same wafer can be sold under different names, at different speeds, and at very different…
silicon validation, first silicon, silicon debug
Chip Bring-Up / Silicon Validation — the process of testing and validating the first fabricated silicon, verifying that the chip functions correctly and meets specifications…
transistor count, moores law, scaling
Moore's Law is the observation, first made by Intel co-founder Gordon Moore in 1965 and revised to its familiar form in 1975, that the number of transistors on an integrated…
transistor count, moores law, scaling
Modern chips contain billions of transistors with Apple M3 having 25 billion and NVIDIA H100 having 80 billion transistors. Feature sizes have shrunk to 3-5 nanometers about 15…
wafer cost, fab cost, economics
Semiconductor Economics: Chip, Wafer, and Fab Costs Overview Semiconductor economics operates across three interconnected cost levels, each driving the next in a hierarchical…
wafer cost, fab cost, economics
Chip cost and fab economics define the massive capital investments and complex cost structures that determine semiconductor pricing — where a leading-edge fab costs 20 billion…
ic design, vlsi, asic design, rtl to gdsii, ppa, timing closure, static timing analysis, architecture, rtl, verification, synthesis, dft, physical design, floorplan, signoff, tapeout, pdk, eda, chiplet
Chip design is the work of turning an intended behaviour into a set of polygons a foundry can print. It proceeds as a ladder of representations — each rung more physical than…
ic design flow, asic design flow, chip design process, vlsi design flow, rtl to gdsii
Chip Design Flow — the end-to-end process for designing an integrated circuit from specification to manufacturing-ready layout (GDSII), encompassing architecture, logic design…
partitioning, block placement, aspect ratio, io placement, hierarchical floor plan
Chip Floorplanning is the high-level placement of major functional blocks (CPU core, cache, memory controller, I/O, analog blocks) and I/O pads — determining overall chip size…
unique id, jtag security, device authentication, chip fingerprint, physically unclonable function puf
Chip ID, Device Authentication, and PUF (Physically Unclonable Function) is the hardware security capability that creates a unique, unforgeable digital identity for each chip die…