Byte-Level Tokenization
nlp
Byte-level tokenization is the tokenization approach that operates on raw byte sequences, enabling complete coverage of arbitrary text inputs - it avoids unknown tokens across…
1,030 technical terms and definitions
nlp
Byte-level tokenization is the tokenization approach that operates on raw byte sequences, enabling complete coverage of arbitrary text inputs - it avoids unknown tokens across…
bpe, byte-level bpe, subword tokenization, tokenizer merge, vocabulary training
Byte pair encoding is a subword vocabulary algorithm that repeatedly merges frequent adjacent symbol pairs. BPE and byte-level variants provide fixed vocabularies, open-text…
tokenization algorithm, sentencepiece tokenizer, unigram language model tokenizer, tokenizer vocabulary
Byte Pair Encoding (BPE) Tokenization is the subword segmentation algorithm that iteratively merges the most frequent pair of adjacent tokens in a training corpus to build…
tokenizer llm, sentencepiece tokenizer, wordpiece tokenization, subword tokenization
Byte Pair Encoding (BPE) and Subword Tokenization is the text segmentation technique that breaks input text into a vocabulary of variable-length subword units — learned…
subword tokenization, bpe vocabulary, sentencepiece tokenizer, wordpiece tokenization
Byte-Pair Encoding (BPE) is the dominant subword tokenization algorithm that iteratively merges the most frequent character pairs to build a vocabulary balancing coverage…
sentencepiece tokenizer, unigram tokenization, wordpiece tokenizer, subword tokenization llm
Byte-Pair Encoding (BPE) Tokenization Variants is a family of subword segmentation algorithms that decompose text into variable-length token units by iteratively merging frequent…
wordpiece tokenizer, sentencepiece tokenizer, subword tokenization, tokenizer vocabulary
Subword Tokenization is the text preprocessing technique that segments input text into a vocabulary of subword units — smaller than whole words but larger than individual…
bytecode intermediate representation, bytecode intermediate, intermediate representation
Bytecode Intermediate Representation Introduction & Motivation Bytecode Intermediate Representation addresses a central problem in programming process control…
byzantine fault tolerance mechanisms, byzantine fault tolerance, fault tolerance mechanisms, byzantine fault, fault tolerance, tolerance mechanisms
Byzantine Fault Tolerance Mechanisms Introduction & Motivation Byzantine Fault Tolerance Mechanisms addresses a central problem in distributed-systems process control…
byzantine fault tolerance pbft, byzantine fault tolerance, fault tolerance pbft, byzantine fault, fault tolerance, tolerance pbft
Byzantine Fault Tolerance PBFT Introduction & Motivation Byzantine Fault Tolerance PBFT addresses a central problem in security-protocols process control…
Multi-Krum and Bulyan Byzantine-Robust Federated Aggregation Introduction & Motivation Multi-Krum and Bulyan Byzantine-Robust Federated Aggregation addresses a central problem…
federated learning
Byzantine-Robust Federated Learning is a federated learning framework designed to tolerate arbitrary malicious behavior from a fraction of participants — ensuring that the global…
Byzantine-Robust Federated Learning Introduction & Motivation Byzantine-Robust Federated Learning addresses a central problem in federated and malicious-client-detection…
charles babbage, difference engine 1822, mechanical calculator history, finite differences, joseph clement engineer, science museum difference engine
Charles Babbage's Difference Engine, designed in 1822, was the first serious attempt to replace human computers with a machine, built to calculate and print mathematical tables…
current mirror design, analog bias, reference circuit, voltage reference
bandgap reference is a circuit that combines voltages with opposing temperature coefficients to produce a supply-insensitive reference near 1.2 volts in silicon. Stable references…
BLC, direct contact DC etch, self aligned contact DRAM, silicon over-recess, contact resistance DRAM
The bitline contact — called BLC or DC (Direct Contact) depending on the maker — etches straight down through nitride and oxide into the exact center of an active area with no…
BL etch, GBL etch, multi-material conductor etch, tungsten polysilicon etch, bitline gate integration
The bitline stack etch — BL Etch or GBL Etch — cuts straight down through a tall sandwich of materials in one continuous pass: a SiN cap on top, then tungsten, then a TiN or WSi…
bitline cap trim etch, SiN cap height correction, secondary trim DRAM, CD correction budget
The BL cap trim is a secondary, targeted etch applied to the SiN cap sitting on top of the bitline stack after the main stack etch has already finished, adjusting that cap's final…
nitride oxide nitride spacer, N O N multilayer spacer, storage node contact self alignment, bitline parasitic capacitance
The bitline spacer etch forms a multilayer nitride-oxide-nitride sidewall around the finished bitline conductor stack, and it is a genuinely different problem from…
BWL etch, WL trench, gate trench DRAM, saddle fin recess, GIDL control, BCAT transistor
The buried wordline trench etch — called BWL Etch, WL Trench, or Gate Trench depending on the maker — carves the channel for a DRAM access transistor's gate down into the silicon…
experimental mos bipolar logic step 3 surface passivated mos structure first working device, atalla kahng mos transistor 1960
Build the First Working MOS Transistor: Atalla and Kahngs Surface-Passivated Structure 1. Why This Specific Structure, Built at Bell Labs in 1959-1960, Finally Worked Mohamed…
grown junction 1951 begin crystal pulling, stefan condition crystal growth interface, withdraw the seed czochralski, grown junction transistor interface velocity
Begin Crystal Pulling: Reversing the Interface from Dissolving to Growing Step nine deliberately dissolved seed material into the melt; step ten has to reverse that exact…
hbm base die, base die, hbm4 base logic die, memory controller die, hbm logic die, custom base die, hbm phy
The base logic die is the bottom die of an HBM stack: the layer that aggregates every TSV column from the DRAM dies above it, runs the physical interface to the host, and handles…
local oxidation of silicon, locos isolation, nitride mask oxidation encroachment
LOCOS Bird's Beak Before shallow trench isolation existed, fabs separated transistors with LOCOS — local oxidation of silicon — and LOCOS had a built-in flaw baked into its own…
mask rom addressing step 10 build a business out, build a business
Build a Business Out of Fixed, Mass-Produced Game Data: the Cartridge ROM 1. Sell a Mask ROM as the Product Itself A game cartridge put a mask-programmed ROM holding a complete…
boson quantum distribution, bose einstein condensation bec, phonon occupancy lattice thermal conductivity, debye heat capacity, photonic stimulated emission, semiconductor quantum statistics
Bose–Einstein Statistics: Bosonic Occupation Physics, Lattice Phonons, and Photonic Quantum Phenomena in Semiconductors Executive Overview Bose–Einstein (BE) statistics governs…
sram six transistor step 2 cross coupled inverter pair, cross coupled inverter bistable latch
Build the Cross-Coupled Inverter Pair as a Bistable Storage Element 2. Build the Cross-Coupled Inverter Pair as a Bistable Storage Element The core of every SRAM cell is not…
tan copper diffusion barrier, amorphous barrier grain boundary, copper seed layer barrier
Tantalum Nitride Diffusion Barrier Copper interconnect only became possible once the industry solved a problem copper itself creates: copper diffuses readily through silicon…
A ball grid array, or BGA, is a chip packaging method that uses a grid of small solder balls on the underside of the package to connect it to a circuit board, replacing…
Backside power delivery is a chip design approach that moves the power distribution network from the front side of the wafer, where signal wiring lives, to the back side, freeing…