c-v curve,metrology
Capacitance-voltage characteristic.
79 technical terms and definitions
Capacitance-voltage characteristic.
IBM flip-chip technology.
Relationship between signal and concentration.
Adjust tool measurements to match known standards.
Measuring tool for length thickness.
Bond cap for protection.
Measure electrical properties of dielectrics and junctions.
Extract doping profile from C-V measurement.
Flow underfill after bonding.
Holds components.
Support wafer for thin wafer processing.
Light emission from electron beam excitation.
Variation in linewidth across wafer or die.
Scanning electron microscope optimized for measuring linewidths.
DIP with ceramic body.
PGA with ceramic substrate.
Use channeling to depth profile.
# Semiconductor Manufacturing Process Chemical Kinetics: Mathematics ## Introduction Semiconductor manufacturing relies heavily on chemical kinetics to control thin film deposition, etching, oxidation, and dopant diffusion. This document provides the mathematical framework underlying these processes. ## Fundamental Kinetic Concepts ### Reaction Rate Expression The general rate expression for a reaction $A + B \rightarrow C$ is: $$ r = k[A]^m[B]^n $$ Where: - $r$ = reaction rate $\left(\frac{\text{mol}}{\text{m}^3 \cdot \text{s}}\right)$ - $k$ = rate constant - $[A], [B]$ = concentrations $\left(\frac{\text{mol}}{\text{m}^3}\right)$ - $m, n$ = reaction orders (empirically determined) ### Arrhenius Equation The temperature dependence of rate constants follows the Arrhenius equation: $$ k = A \exp\left(-\frac{E_a}{RT}\right) $$ Where: - $A$ = pre-exponential factor (frequency factor) - $E_a$ = activation energy $\left(\frac{\text{J}}{\text{mol}}\right)$ - $R$ = universal gas constant $\left(8.314 \frac{\text{J}}{\text{mol} \cdot \text{K}}\right)$ - $T$ = absolute temperature (K) **Linearized Form (for Arrhenius plots):** $$ \ln(k) = \ln(A) - \frac{E_a}{R} \cdot \frac{1}{T} $$ ## Chemical Vapor Deposition (CVD) ### Overall Rate Model CVD involves both gas-phase transport and surface reaction. The overall deposition rate is: $$ R = \frac{C_g}{\frac{1}{h_g} + \frac{1}{k_s}} $$ Where: - $R$ = deposition rate $\left(\frac{\text{mol}}{\text{m}^2 \cdot \text{s}}\right)$ - $C_g$ = gas-phase reactant concentration - $h_g$ = gas-phase mass transfer coefficient $\left(\frac{\text{m}}{\text{s}}\right)$ - $k_s$ = surface reaction rate constant $\left(\frac{\text{m}}{\text{s}}\right)$ ### Regime Analysis **Surface-Reaction Limited** (low temperature, $k_s \ll h_g$): $$ R \approx k_s \cdot C_g = A \exp\left(-\frac{E_a}{RT}\right) \cdot C_g $$ **Mass-Transport Limited** (high temperature, $h_g \ll k_s$): $$ R \approx h_g \cdot C_g $$ ### Mass Transfer Coefficient For laminar flow over a flat plate: $$ h_g = \frac{D_{AB}}{L} \cdot 0.664 \cdot Re_L^{1/2} \cdot Sc^{1/3} $$ Where: - $D_{AB}$ = binary diffusion coefficient - $L$ = characteristic length - $Re_L = \frac{\rho v L}{\mu}$ = Reynolds number - $Sc = \frac{\mu}{\rho D_{AB}}$ = Schmidt number ## Thermal Oxidation: Deal-Grove Model ### Governing Equation The Deal-Grove model describes silicon oxidation ($\text{Si} + \text{O}_2 \rightarrow \text{SiO}_2$): $$ x^2 + Ax = B(t + \tau) $$ Where: - $x$ = oxide thickness (m) - $t$ = oxidation time (s) - $\tau$ = initial time correction (accounts for native oxide) ### Rate Constants **Linear Rate Constant:** $$ \frac{B}{A} = \frac{k_s C^*}{N_{ox}} $$ **Parabolic Rate Constant:** $$ B = \frac{2D_{eff} C^*}{N_{ox}} $$ Where: - $D_{eff}$ = effective diffusion coefficient of oxidant through oxide - $C^*$ = equilibrium oxidant concentration in oxide - $N_{ox}$ = number of oxidant molecules incorporated per unit volume of oxide - $k_s$ = surface reaction rate constant ### Limiting Cases **Thin Oxide Regime** (short times, $x \ll A$): $$ x \approx \frac{B}{A}(t + \tau) $$ - Linear growth (surface-reaction controlled) **Thick Oxide Regime** (long times, $x \gg A$): $$ x \approx \sqrt{B \cdot t} $$ - Parabolic growth (diffusion controlled) ### Explicit Solution Solving the quadratic equation: $$ x = \frac{A}{2}\left[\sqrt{1 + \frac{4B(t+\tau)}{A^2}} - 1\right] $$ ## Plasma Etching Kinetics ### Ion-Enhanced Etching Model The etch rate combines thermal and ion-assisted components: $$ R = k_{thermal} \cdot P \cdot \exp\left(-\frac{E_a}{RT}\right) + k_{ion} \cdot \Gamma_{ion}^\alpha \cdot \theta $$ Where: - $k_{thermal}$ = thermal etching rate constant - $P$ = reactive gas partial pressure - $\Gamma_{ion}$ = ion flux $\left(\frac{\text{ions}}{\text{m}^2 \cdot \text{s}}\right)$ - $\alpha$ = ion flux exponent (typically 0.5–1.5) - $\theta$ = surface coverage of reactive species ### Sputter Yield Model Physical sputtering rate: $$ R_{sputter} = Y(\theta, E) \cdot \frac{\Gamma_{ion}}{n} $$ Where: - $Y$ = sputter yield (atoms removed per incident ion) - $E$ = ion energy - $\theta$ = ion incidence angle - $n$ = atomic density of target material ### Selectivity Selectivity between materials A and B: $$ S = \frac{R_A}{R_B} $$ ## Surface Reaction Kinetics ### Langmuir Adsorption Isotherm For single-species adsorption at equilibrium: $$ \theta = \frac{K \cdot P}{1 + K \cdot P} $$ Where: - $\theta$ = fractional surface coverage $(0 \leq \theta \leq 1)$ - $K$ = adsorption equilibrium constant - $P$ = partial pressure **Temperature Dependence of K:** $$ K = K_0 \exp\left(\frac{-\Delta H_{ads}}{RT}\right) $$ ### Multi-Species Competitive Adsorption For species A and B competing for the same sites: $$ \theta_A = \frac{K_A P_A}{1 + K_A P_A + K_B P_B} $$ $$ \theta_B = \frac{K_B P_B}{1 + K_A P_A + K_B P_B} $$ ### Surface Reaction Rate **Langmuir-Hinshelwood Mechanism** (both reactants adsorbed): $$ r = k_s \cdot \theta_A \cdot \theta_B = k_s \cdot \frac{K_A P_A \cdot K_B P_B}{(1 + K_A P_A + K_B P_B)^2} $$ **Eley-Rideal Mechanism** (one reactant from gas phase): $$ r = k_s \cdot \theta_A \cdot P_B = k_s \cdot \frac{K_A P_A \cdot P_B}{1 + K_A P_A} $$ ### Limiting Behavior | Condition | Rate Expression | Order | |-----------|-----------------|-------| | $K \cdot P \ll 1$ | $r \approx k_s K P$ | First-order | | $K \cdot P \gg 1$ | $r \approx k_s$ | Zero-order | ## Diffusion Processes ### Fick's Laws **First Law** (steady-state flux): $$ J = -D \frac{\partial C}{\partial x} $$ **Second Law** (transient diffusion): $$ \frac{\partial C}{\partial t} = D \frac{\partial^2 C}{\partial x^2} $$ For 3D: $$ \frac{\partial C}{\partial t} = D \nabla^2 C = D \left(\frac{\partial^2 C}{\partial x^2} + \frac{\partial^2 C}{\partial y^2} + \frac{\partial^2 C}{\partial z^2}\right) $$ ### Concentration-Dependent Diffusion For dopants where $D = D(C)$: $$ \frac{\partial C}{\partial t} = \frac{\partial}{\partial x}\left[D(C) \frac{\partial C}{\partial x}\right] $$ ### Analytical Solutions **Constant Surface Concentration** (semi-infinite medium): $$ C(x,t) = C_s \cdot \text{erfc}\left(\frac{x}{2\sqrt{Dt}}\right) $$ Where $\text{erfc}$ is the complementary error function: $$ \text{erfc}(z) = 1 - \text{erf}(z) = 1 - \frac{2}{\sqrt{\pi}}\int_0^z e^{-u^2} du $$ **Fixed Total Dose** (Gaussian profile): $$ C(x,t) = \frac{Q}{\sqrt{\pi D t}} \exp\left(-\frac{x^2}{4Dt}\right) $$ Where $Q$ = total dose $\left(\frac{\text{atoms}}{\text{m}^2}\right)$ ### Diffusion Coefficient Temperature Dependence $$ D = D_0 \exp\left(-\frac{E_a}{kT}\right) $$ Where $k = 8.617 \times 10^{-5} \frac{\text{eV}}{\text{K}}$ (Boltzmann constant) ## Reactor-Scale Modeling ### Species Conservation Equation The convection-diffusion-reaction equation: $$ \frac{\partial C_i}{\partial t} + \nabla \cdot (\mathbf{v} C_i) = \nabla \cdot (D_i \nabla C_i) + R_i $$ Expanded form: $$ \frac{\partial C_i}{\partial t} + \mathbf{v} \cdot \nabla C_i = D_i \nabla^2 C_i + R_i $$ ### Coupled Equations **Navier-Stokes (momentum):** $$ \rho \left(\frac{\partial \mathbf{v}}{\partial t} + \mathbf{v} \cdot \nabla \mathbf{v}\right) = -\nabla P + \mu \nabla^2 \mathbf{v} + \rho \mathbf{g} $$ **Continuity (mass):** $$ \frac{\partial \rho}{\partial t} + \nabla \cdot (\rho \mathbf{v}) = 0 $$ **Energy:** $$ \rho c_p \left(\frac{\partial T}{\partial t} + \mathbf{v} \cdot \nabla T\right) = k \nabla^2 T + Q_{rxn} $$ Where $Q_{rxn} = \sum_j (-\Delta H_j) r_j$ is the heat of reaction. ### Boundary Conditions **Surface reaction flux:** $$ -D_i \frac{\partial C_i}{\partial n}\bigg|_{surface} = R_{s,i} $$ **Inlet conditions:** $$ C_i = C_{i,inlet}, \quad T = T_{inlet}, \quad \mathbf{v} = \mathbf{v}_{inlet} $$ ## Dimensionless Analysis ### Damköhler Number $$ Da = \frac{\text{reaction rate}}{\text{transport rate}} = \frac{k_s L}{D} $$ | Da Value | Regime | Characteristics | |----------|--------|-----------------| | $Da \gg 1$ | Reaction-limited | Uniform deposition, strong T dependence | | $Da \ll 1$ | Transport-limited | Non-uniform, weak T dependence | ### Thiele Modulus For reactions in porous structures: $$ \phi = L \sqrt{\frac{k}{D_{eff}}} $$ **Effectiveness Factor:** $$ \eta = \frac{\tanh(\phi)}{\phi} $$ ### Peclet Number $$ Pe = \frac{vL}{D} = \frac{\text{convective transport}}{\text{diffusive transport}} $$ ### Stanton Number $$ St = \frac{h}{\rho v c_p} = \frac{\text{heat transfer}}{\text{thermal capacity of flow}} $$ ## Advanced Modeling Techniques ### Microkinetic Modeling System of coupled ODEs for surface species: $$ \frac{d\theta_i}{dt} = \sum_j \left[\nu_{ij}^+ r_j^+ - \nu_{ij}^- r_j^-\right] $$ Where: - $\theta_i$ = coverage of species $i$ - $\nu_{ij}$ = stoichiometric coefficient - $r_j^+, r_j^-$ = forward and reverse rates of reaction $j$ **Example: Adsorption-Desorption-Reaction:** $$ \frac{d\theta_A}{dt} = k_{ads} P_A (1-\theta_A-\theta_B) - k_{des} \theta_A - k_{rxn} \theta_A \theta_B $$ ### Stochastic Methods **Kinetic Monte Carlo (KMC):** Transition rates: $$ W_i = \nu_i \exp\left(-\frac{E_i}{kT}\right) $$ Time step: $$ \Delta t = -\frac{\ln(r)}{\sum_i W_i} $$ Where $r \in (0,1]$ is a random number. **Master Equation:** $$ \frac{dP_n}{dt} = \sum_m \left[W_{mn} P_m - W_{nm} P_n\right] $$ ### Multi-Scale Coupling | Scale | Size | Method | Output | |-------|------|--------|--------| | Quantum | ~Å | DFT | Reaction barriers, adsorption energies | | Atomic | ~nm | MD, KMC | Surface morphology, growth modes | | Feature | ~$\mu$m | Level-set, FEM | Profile evolution | | Reactor | ~cm | CFD | Uniformity, gas dynamics | ## Computational Methods ### Numerical Discretization **Finite Difference (1D diffusion):** $$ \frac{C_i^{n+1} - C_i^n}{\Delta t} = D \frac{C_{i+1}^n - 2C_i^n + C_{i-1}^n}{(\Delta x)^2} $$ **Stability Criterion (explicit method):** $$ \frac{D \Delta t}{(\Delta x)^2} \leq \frac{1}{2} $$ ### Operator Splitting For stiff reaction-diffusion systems: 1. **Diffusion step:** Solve $\frac{\partial C}{\partial t} = D \nabla^2 C$ for $\Delta t/2$ 2. **Reaction step:** Solve $\frac{dC}{dt} = R(C)$ for $\Delta t$ 3. **Diffusion step:** Solve $\frac{\partial C}{\partial t} = D \nabla^2 C$ for $\Delta t/2$ ### Newton-Raphson for Nonlinear Systems $$ \mathbf{x}^{(k+1)} = \mathbf{x}^{(k)} - \mathbf{J}^{-1}(\mathbf{x}^{(k)}) \cdot \mathbf{F}(\mathbf{x}^{(k)}) $$ Where $\mathbf{J}$ is the Jacobian matrix: $$ J_{ij} = \frac{\partial F_i}{\partial x_j} $$ ## Key Equations Summary ### Rate Expressions | Process | Equation | |---------|----------| | Arrhenius | $k = A \exp\left(-\frac{E_a}{RT}\right)$ | | CVD Rate | $R = \frac{C_g}{1/h_g + 1/k_s}$ | | Deal-Grove | $x^2 + Ax = B(t + \tau)$ | | Langmuir | $\theta = \frac{KP}{1+KP}$ | | Fick's 2nd Law | $\frac{\partial C}{\partial t} = D \frac{\partial^2 C}{\partial x^2}$ | ### Dimensionless Numbers | Number | Definition | Physical Meaning | |--------|------------|------------------| | Damköhler ($Da$) | $\frac{k_s L}{D}$ | Reaction vs. transport rate | | Thiele ($\phi$) | $L\sqrt{k/D_{eff}}$ | Reaction-diffusion penetration | | Peclet ($Pe$) | $\frac{vL}{D}$ | Convection vs. diffusion | | Reynolds ($Re$) | $\frac{\rho vL}{\mu}$ | Inertial vs. viscous forces |
Polishing for cross-sections.
Resist using acid catalysis for high sensitivity.
# Chip Complexity and Moore's Law: Mathematical Modeling in Semiconductor Manufacturing ## 1. The Core Exponential Model of Moore's Law ### 1.1 Fundamental Expression The foundational mathematical expression of Moore's Law describes transistor count as an exponential function of time: $$ N(t) = N_0 \cdot 2^{\frac{t}{T_d}} $$ **Variable Definitions:** - $N(t)$ — Transistor count at time $t$ - $N_0$ — Initial transistor count (reference point) - $T_d$ — Doubling period - Original (1965): $T_d \approx 12$ months - Revised (1975): $T_d \approx 24$ months ### 1.2 Continuous Form In continuous exponential form: $$ N(t) = N_0 \cdot e^{rt} $$ Where the continuous growth rate constant is: $$ r = \frac{\ln(2)}{T_d} $$ ### 1.3 Stepwise Exponential Model For modeling different technological phases: $$ T_i(t) = T_{i,0} \cdot e^{r_i(t - \tau_i)} $$ **Where:** - $T_i$ — Transistor density in phase $i$ - $r_i$ — Growth rate constant for phase $i$ - $\tau_i$ — Start time of phase $i$ **Doubling time calculation:** $$ t_2 = \frac{\ln(2)}{r_i} $$ ### 1.4 Key Historical Data Points | Year | Processor | Transistor Count | Process Node | |------|-----------|------------------|--------------| | 1971 | Intel 4004 | $2.3 \times 10^3$ | 10 µm | | 1989 | Intel 486 | $1.2 \times 10^6$ | 1 µm | | 2000 | Pentium 4 | $4.2 \times 10^7$ | 180 nm | | 2010 | Core i7 | $1.17 \times 10^9$ | 32 nm | | 2020 | Apple M1 | $1.6 \times 10^{10}$ | 5 nm | | 2025 | NVIDIA GB202 | $9.2 \times 10^{10}$ | 4 nm | ## 2. Dennard Scaling: The Power-Performance Equations ### 2.1 Fundamental Scaling Relationships For a scaling factor $S > 1$ (shrinking dimensions): **Dimensional Scaling:** $$ L \propto S^{-1}, \quad W \propto S^{-1}, \quad t_{ox} \propto S^{-1} $$ **Voltage and Threshold Scaling:** $$ V_{DD} \propto S^{-1}, \quad V_T \propto S^{-1} $$ **Doping Concentration (inverse scaling):** $$ N_A \propto S $$ ### 2.2 CMOS Power Model Total power consumption in CMOS circuits: $$ P_{total} = P_{dynamic} + P_{static} $$ **Dynamic Power:** $$ P_{dynamic} = \alpha \cdot C \cdot V_{DD}^2 \cdot f $$ **Where:** - $\alpha$ — Activity factor (switching probability) - $C$ — Load capacitance - $V_{DD}$ — Supply voltage - $f$ — Clock frequency **Static Power (Leakage):** $$ P_{static} = V_{DD} \cdot I_{leak} $$ **Complete Power Model:** $$ P = Q \cdot f \cdot C \cdot V^2 + V \cdot I_{leak} $$ Where $Q$ = number of transistors. ### 2.3 Dennard Scaling Predictions per Generation | Parameter | Symbol | Scaling Factor | Change | |-----------|--------|----------------|--------| | Linear dimensions | $L, W, t_{ox}$ | $0.7\times$ | −30% | | Device area | $A$ | $0.5\times$ | −50% | | Capacitance | $C$ | $0.7\times$ | −30% | | Voltage | $V_{DD}$ | $0.7\times$ | −30% | | Current | $I$ | $0.7\times$ | −30% | | Delay | $\tau$ | $0.7\times$ | −30% | | Frequency | $f$ | $1.4\times$ | +40% | | Power per transistor | $P/N$ | $0.5\times$ | −50% | | **Power density** | $P/A$ | $1.0\times$ | **Constant** | ### 2.4 Derived Relationships **Capacitance-Voltage-Frequency Relationship:** Since $C \propto \frac{\epsilon \cdot A}{t_{ox}}$ and both $A$ and $t_{ox}$ scale as $S^{-2}$ and $S^{-1}$ respectively: $$ C \propto S^{-1} $$ **Power Scaling:** $$ P = C \cdot V^2 \cdot f \propto S^{-1} \cdot S^{-2} \cdot S^{1} = S^{-2} $$ **Power Density:** $$ \frac{P}{A} \propto \frac{S^{-2}}{S^{-2}} = 1 \quad \text{(constant)} $$ ## 3. Lithography Resolution Limits: The Rayleigh Equation ### 3.1 Fundamental Resolution Criterion The Rayleigh criterion for optical lithography: $$ CD = k_1 \cdot \frac{\lambda}{NA} $$ **Variable Definitions:** - $CD$ — Critical dimension (minimum feature size) - $\lambda$ — Wavelength of light source - $NA$ — Numerical aperture of the optical system - $k_1$ — Process-dependent coefficient ($0.25 \leq k_1 \leq 1.0$) ### 3.2 Physical Limits **Theoretical minimum ($k_1 = 0.25$):** $$ CD_{min} = 0.25 \cdot \frac{\lambda}{NA} $$ **For 193nm immersion lithography ($NA_{max} = 1.35$):** $$ CD_{min} = 0.25 \cdot \frac{193 \text{ nm}}{1.35} \approx 36 \text{ nm} $$ **For EUV lithography ($\lambda = 13.5$ nm, $NA = 0.55$):** $$ CD_{min} = 0.25 \cdot \frac{13.5 \text{ nm}}{0.55} \approx 6.1 \text{ nm} $$ ### 3.3 Depth of Focus $$ DOF = k_2 \cdot \frac{\lambda}{NA^2} $$ **Where:** - $k_2$ — Process-dependent coefficient ($0.4 \leq k_2 \leq 1.0$) **Resolution-DOF Trade-off:** $$ CD \cdot DOF \propto \frac{\lambda^2}{NA^3} $$ ### 3.4 Half-Pitch Resolution For dense line/space patterns: $$ \text{Half-pitch}_{min} = \frac{k_1 \cdot \lambda}{NA} $$ **Abbe criterion (absolute limit):** $$ \text{Half-pitch}_{absolute} = \frac{0.25 \cdot \lambda}{NA} $$ ### 3.5 Lithography Technology Comparison | Technology | Wavelength ($\lambda$) | NA | $k_1$ (practical) | Min. Pitch | |------------|------------------------|-----|-------------------|------------| | i-line | 365 nm | 0.6 | 0.4 | 243 nm | | KrF DUV | 248 nm | 0.8 | 0.35 | 108 nm | | ArF DUV | 193 nm | 0.93 | 0.3 | 62 nm | | ArF Immersion | 193 nm | 1.35 | 0.28 | 40 nm | | EUV | 13.5 nm | 0.33 | 0.4 | 16 nm | | High-NA EUV | 13.5 nm | 0.55 | 0.35 | 8.6 nm | ## 4. Multi-Logistic Growth Model: Beyond Simple Exponentials ### 4.1 Limitations of Simple Exponential Empirical observations show: - Heteroscedasticity in transistor density data - Autocorrelation in residuals - Multiple inflection points in growth curves ### 4.2 Single Logistic Model $$ T(t) = \frac{K}{1 + e^{-r(t - \tau)}} $$ **Where:** - $K$ — Carrying capacity (saturation level) - $r$ — Intrinsic growth rate - $\tau$ — Time of inflection point (half-saturation) ### 4.3 Generalized Multi-Logistic Model For $n$ consecutive waves of technological development: $$ T(t) = \sum_{i=1}^{n} \frac{K_i}{1 + e^{-r_i(t - \tau_i)}} $$ **Parameters per phase $i$:** - $r_i$ — Intrinsic growth rate constant - $K_i$ — Saturation level for phase $i$ - $\tau_i$ — Characteristic time (midpoint) ### 4.4 Bi-Logistic Model (Observed in Intel Data) $$ T(t) = \frac{K_1}{1 + e^{-r_1(t - \tau_1)}} + \frac{K_2}{1 + e^{-r_2(t - \tau_2)}} $$ **Empirical findings:** - Phase 1 doubling time: $\approx 17$ months - Phase 2 doubling time: $\approx 33$ months - Characteristic times: $\tau \approx 9.5$ years per phase ### 4.5 Six-Wave Model Research identifies six distinct S-curves in transistor density evolution: $$ T(t) = \sum_{i=1}^{6} \frac{K_i}{1 + e^{-r_i(t - \tau_i)}} $$ **Pattern per wave:** - Rapid growth: ~6 years (10× density increase) - Plateau/consolidation: ~3 years - Transition to next wave ### 4.6 Growth Rate Dynamics The instantaneous growth rate: $$ \frac{dT}{dt} = r \cdot T \cdot \left(1 - \frac{T}{K}\right) $$ **Maximum growth rate occurs at:** $$ T^* = \frac{K}{2} \quad \text{(inflection point)} $$ ## 5. Wright's Law: Experience Curve Economics ### 5.1 Fundamental Relationship Cost as a function of cumulative production: $$ C(X) = C_0 \cdot X^{-\alpha} $$ **Where:** - $C(X)$ — Cost per unit at cumulative production $X$ - $C_0$ — Cost of first unit produced - $\alpha$ — Learning parameter (learning exponent) ### 5.2 Learning Rate The fractional cost reduction per doubling of cumulative production: $$ \text{Learning Rate} = 1 - 2^{-\alpha} $$ **Typical values for semiconductors:** - $\alpha \approx 0.2 - 0.35$ - Learning rate $\approx 13\% - 22\%$ ### 5.3 Log-Linear Form Taking logarithms: $$ \log C = \log C_0 - \alpha \cdot \log X $$ This produces a straight line on log-log axes. ### 5.4 Connection to Moore's Law When cumulative production grows exponentially: $$ X(t) = X_0 \cdot e^{gt} $$ Then: $$ C(t) = C_0 \cdot (X_0 \cdot e^{gt})^{-\alpha} = C_0 \cdot X_0^{-\alpha} \cdot e^{-\alpha g t} $$ **Key insight:** Wright's Law and Moore's Law produce equivalent forecasts when: $$ \log X \propto t \quad \text{(exponential production growth)} $$ ### 5.5 Price Decline Model For technologies following Wright's Law: $$ P(X) = P_0 \cdot \left(\frac{X}{X_0}\right)^{-\alpha} $$ **Example: Solar PV** - Learning rate: ~20% per doubling - $\alpha \approx 0.32$ ### 5.6 Semiconductor-Specific Learning **Cost per transistor decline:** $$ \frac{C}{N}(t) = \left(\frac{C}{N}\right)_0 \cdot e^{-\lambda t} $$ Where $\lambda$ captures combined effects of: - Increased transistor density - Manufacturing yield improvements - Process optimization ## 6. Rock's Law (Moore's Second Law): Fab Cost Escalation ### 6.1 Capital Cost Growth The cost of semiconductor fabrication facilities grows exponentially: $$ C_{fab}(t) = C_0 \cdot 2^{\frac{t}{T_{fab}}} $$ **Where:** - $C_{fab}(t)$ — Fab cost at time $t$ - $C_0$ — Reference fab cost - $T_{fab} \approx 4$ years (doubling period) ### 6.2 Continuous Form $$ C_{fab}(t) = C_0 \cdot e^{r_{fab} \cdot t} $$ Where: $$ r_{fab} = \frac{\ln(2)}{T_{fab}} \approx 0.173 \text{ per year} $$ ### 6.3 Equipment Cost Scaling Lithography tool cost escalation: $$ C_{litho}(n) = C_{litho,0} \cdot 2^{n/2} $$ Where $n$ = number of technology nodes advanced. **Example costs (2024):** - ArF immersion scanner: ~$100M - EUV scanner: ~$200M - High-NA EUV scanner: ~$400M ### 6.4 Economic Sustainability Condition For continued scaling, cost reduction must outpace fab cost increase: $$ \frac{d}{dt}\left(\frac{C_{fab}}{N \cdot Y}\right) < 0 $$ Where: - $N$ — Transistors per chip - $Y$ — Manufacturing yield This requires: $$ \frac{d N}{dt} + \frac{d Y}{dt} > \frac{d C_{fab}}{dt} $$ ## 7. Quantum Tunneling Limits: The Physical Boundary ### 7.1 Tunneling Probability For a rectangular potential barrier: $$ T \approx \exp\left(-2\kappa d\right) $$ **Where the decay constant:** $$ \kappa = \frac{\sqrt{2m^*(U - E)}}{\hbar} $$ **Variables:** - $d$ — Barrier thickness - $U$ — Barrier height (potential energy) - $E$ — Electron kinetic energy - $m^*$ — Effective electron mass - $\hbar$ — Reduced Planck constant ### 7.2 WKB Approximation For arbitrary barrier shapes $U(x)$: $$ T \approx \exp\left(-\frac{2}{\hbar}\int_{x_1}^{x_2}\sqrt{2m^*(U(x) - E)} \, dx\right) $$ ### 7.3 Gate Oxide Tunneling Current Direct tunneling current density through gate oxide: $$ J_g = A \cdot E_{ox}^2 \cdot \exp\left(-\frac{B}{E_{ox}}\right) $$ **Where:** $$ B = \frac{4\sqrt{2m^*}\phi_B^{3/2}}{3q\hbar} $$ **Variables:** - $E_{ox}$ — Electric field across oxide - $\phi_B$ — Barrier height - $m^*$ — Effective mass in oxide - $q$ — Electron charge ### 7.4 Fowler-Nordheim Tunneling For thicker oxides under high fields: $$ J_{FN} = \frac{q^3 E_{ox}^2}{16\pi^2\hbar\phi_B} \cdot \exp\left(-\frac{4\sqrt{2m^*}\phi_B^{3/2}}{3q\hbar E_{ox}}\right) $$ ### 7.5 Subthreshold Swing Limit Thermal limit on switching steepness: $$ SS_{min} = \frac{kT}{q} \cdot \ln(10) \approx 60 \text{ mV/decade} \quad \text{(at 300K)} $$ **Temperature dependence:** $$ SS_{min}(T) = \frac{kT \cdot \ln(10)}{q} = 2.3 \cdot \frac{kT}{q} $$ ### 7.6 Physical Size Limits **Gate oxide thickness limit:** $$ t_{ox,min} \approx 1 \text{ nm} $$ **Channel length limit (conventional MOSFET):** $$ L_{ch,min} \approx 1-3 \text{ nm} $$ **Limiting factors:** - Direct source-drain tunneling - Gate oxide tunneling - Quantum confinement effects - Statistical dopant fluctuation ### 7.7 Source-Drain Tunneling Leakage current due to direct tunneling: $$ I_{SD,tunnel} \propto \exp\left(-\frac{2L_{ch}}{\lambda}\right) $$ Where $\lambda$ is the characteristic tunneling length: $$ \lambda = \frac{\hbar}{\sqrt{2m^*E_g}} $$ ## 8. The Breakdown of Dennard Scaling (Post-2006) ### 8.1 Voltage Scaling Limit Threshold voltage cannot scale below: $$ V_T > \frac{kT}{q} \cdot \ln\left(\frac{I_{on}}{I_{off}}\right) \cdot \frac{1}{n} $$ **Where:** - $n$ — Subthreshold ideality factor (~1.0-1.5) - $I_{on}/I_{off}$ — Required on/off current ratio (~$10^6$) **Practical minimum:** $$ V_T \gtrsim 0.2-0.3 \text{ V} $$ ### 8.2 Leakage Current Growth Subthreshold leakage scales exponentially with $V_T$: $$ I_{off} \propto \exp\left(-\frac{qV_T}{nkT}\right) $$ As $V_T$ decreases, leakage increases exponentially. ### 8.3 Post-Dennard Power Density After Dennard scaling breakdown (~65nm node, ~2006): $$ \frac{P}{A} \propto S^{\beta} \quad \text{where } \beta \approx 0.5 - 1.0 $$ **Power density increase per generation:** $$ \Delta\left(\frac{P}{A}\right) \approx 1.2\times - 1.5\times $$ ### 8.4 Dark Silicon Fraction of chip that can be active simultaneously: $$ f_{active} = \frac{P_{budget}}{P_{density} \cdot A_{chip}} $$ As power density increases, $f_{active}$ decreases: $$ f_{active}(n) \approx f_0 \cdot S^{-\beta n} $$ Where $n$ = number of generations past Dennard breakdown. ### 8.5 Utilization Wall Maximum useful transistor utilization: $$ U_{max} = \frac{P_{TDP}}{P_{transistor} \cdot N} $$ **Trend:** $$ U_{max}(t) \propto 2^{-t/T_U} $$ Where $T_U \approx 2-3$ years. ## 9. Koomey's Law: Energy Efficiency Scaling ### 9.1 Performance per Watt Computations per joule of energy: $$ \eta(t) = \eta_0 \cdot 2^{\frac{t}{T_K}} $$ **Historical doubling period:** $$ T_K \approx 1.5 \text{ years} $$ ### 9.2 Derivation from Moore + Dennard During Dennard era: - Transistor count: $N \propto 2^{t/2}$ (Moore, 2-year doubling) - Power constant: $P = \text{const}$ (Dennard) - Performance $\propto N$ Therefore: $$ \frac{\text{Performance}}{P} \propto 2^{t/2} $$ With frequency scaling ($f \propto 1.4^{t/2}$): $$ \frac{\text{Computations}}{J} \propto 2^{t/1.5} $$ ### 9.3 Post-Dennard Koomey Scaling After 2006, efficiency gains slow: $$ T_K \approx 2.5 - 3 \text{ years} $$ ### 9.4 Energy per Operation $$ E_{op}(t) = E_0 \cdot 2^{-t/T_K} $$ **Minimum energy per bit operation (Landauer limit):** $$ E_{min} = kT \cdot \ln(2) \approx 2.9 \times 10^{-21} \text{ J} \quad \text{(at 300K)} $$ ## 10. Integrated Economic Model ### 10.1 Cost per Transistor $$ \frac{C_{chip}}{N} = \frac{C_{wafer}}{Y \cdot A_{die} \cdot \rho} $$ **Where:** - $C_{wafer}$ — Wafer processing cost - $Y$ — Yield (fraction of good dice) - $A_{die}$ — Die area - $\rho$ — Transistor density (transistors/mm²) ### 10.2 Yield Models **Poisson (defect-limited) model:** $$ Y = e^{-D_0 \cdot A_{die}} $$ **Murphy's model:** $$ Y = \left(\frac{1 - e^{-D_0 \cdot A_{die}}}{D_0 \cdot A_{die}}\right)^2 $$ **Seeds' model:** $$ Y = e^{-\sqrt{D_0 \cdot A_{die}}} $$ ### 10.3 Learning Curve Yield Model Yield improvement with cumulative production: $$ Y(X) = Y_{\infty} - (Y_{\infty} - Y_0) \cdot e^{-\gamma X} $$ **Or power law form:** $$ Y(X) = Y_0 \cdot X^{\beta} $$ ### 10.4 Die Cost Model $$ C_{die} = \frac{C_{wafer}}{\pi \cdot (D/2)^2 / A_{die} \cdot Y} $$ Where $D$ = wafer diameter. **Usable dice per wafer (approximate):** $$ N_{dice} \approx \frac{\pi D^2}{4 A_{die}} - \frac{\pi D}{\sqrt{2 A_{die}}} $$ ### 10.5 Cost per Function (Moore's Original Metric) $$ C_f(n) = C_{f,0} \cdot 2^{-n} $$ Where $n$ = number of Moore's Law generations. **Moore's condition for sustainable scaling:** $$ \frac{\Delta C_f}{C_f} \leq -30\% \text{ per transistor doubling} $$ ### 10.6 Total Cost of Ownership $$ TCO = C_{fab} + C_{equipment} + C_{materials} + C_{labor} + C_{yield\_loss} $$ **Normalized per transistor:** $$ \frac{TCO}{N_{total}} = \frac{C_{fab}/L_{fab} + C_{wafer} \cdot W_{annual}}{N_{die} \cdot D_{annual} \cdot Y} $$ Where: - $L_{fab}$ — Fab lifetime (years) - $W_{annual}$ — Annual wafer starts - $D_{annual}$ — Annual die output ## 11. The Mathematical Ecosystem ### 11.1 Interconnected Relationships ``` - ┌─────────────────────────────────────────────────────────────┐ │ MOORE'S LAW │ │ N(t) = N₀ \cdot 2^(t/Td) │ │ (Exponential transistor growth) │ └─────────────────────┬───────────────────────────────────────┘ │ ▼ ┌─────────────────────────────────────────────────────────────┐ │ DENNARD SCALING │ │ P/A = constant (ideal) │ │ [BROKEN c. 2006 at ~65nm node] │ └─────────────────────┬───────────────────────────────────────┘ │ ▼ ┌─────────────────────────────────────────────────────────────┐ │ LITHOGRAPHY LIMITS │ │ CD = k₁ \cdot λ/NA │ │ (Rayleigh criterion, k₁ ≥ 0.25) │ └─────────────────────┬───────────────────────────────────────┘ │ ▼ ┌─────────────────────────────────────────────────────────────┐ │ QUANTUM LIMITS │ │ T ∝ exp(-2κd), tunneling │ │ (Physical limit ~1-3 nm) │ └─────────────────────┬───────────────────────────────────────┘ │ ▼ ┌─────────────────────────────────────────────────────────────┐ │ ECONOMIC CONSTRAINTS │ │ Rock's Law: C_fab ∝ 2^(t/4) │ │ Wright's Law: C ∝ X^(-α) │ └─────────────────────────────────────────────────────────────┘ ``` ### 11.2 Equations | Law/Model | Equation | Domain | |-----------|----------|--------| | Moore's Law | $N(t) = N_0 \cdot 2^{t/T_d}$ | Transistor count | | Dennard Scaling | $P/A = \text{const}$ | Power density | | Rayleigh Criterion | $CD = k_1 \lambda / NA$ | Lithography | | Tunneling | $T \sim e^{-2\kappa d}$ | Quantum limit | | Wright's Law | $C = C_0 X^{-\alpha}$ | Learning curve | | Rock's Law | $C_{fab} = C_0 \cdot 2^{t/4}$ | Fab cost | | Koomey's Law | $\eta = \eta_0 \cdot 2^{t/1.5}$ | Efficiency | ### 11.3 Current State (2025) **Transition from 1D to multi-dimensional scaling:** $$ \text{Performance} = f(\text{density}, \text{architecture}, \text{packaging}, \text{software}) $$ **"More than Moore" approach:** $$ \text{Value} \neq \text{Transistor Count} $$ Instead: $$ \text{Value} = \int \text{(Functionality × Efficiency × Integration)} \, d(\text{innovation}) $$ ## Physical Constants | Constant | Symbol | Value | |----------|--------|-------| | Boltzmann constant | $k$ | $1.381 \times 10^{-23}$ J/K | | Elementary charge | $q$ | $1.602 \times 10^{-19}$ C | | Planck constant | $h$ | $6.626 \times 10^{-34}$ J\cdots | | Reduced Planck | $\hbar$ | $1.055 \times 10^{-34}$ J\cdots | | Electron mass | $m_e$ | $9.109 \times 10^{-31}$ kg | | Thermal voltage (300K) | $kT/q$ | 25.9 mV | ## Technology Node Progression | Node Name | Year | Gate Length | Density (MTr/mm²) | |-----------|------|-------------|-------------------| | 180 nm | 1999 | 130 nm | 1.7 | | 130 nm | 2001 | 90 nm | 3.3 | | 90 nm | 2003 | 50 nm | 6.5 | | 65 nm | 2005 | 35 nm | 13 | | 45 nm | 2007 | 25 nm | 26 | | 32 nm | 2009 | 20 nm | 52 | | 22 nm | 2012 | 14 nm | 100 | | 14 nm | 2014 | 10 nm | 170 | | 10 nm | 2016 | 7 nm | 280 | | 7 nm | 2018 | 5 nm | 450 | | 5 nm | 2020 | 3.5 nm | 700 | | 3 nm | 2022 | 2.5 nm | 1100 | | 2 nm | 2025 | 1.8 nm | 1700 |
# Chip Complexity and Moore's Law: Mathematical Modeling in Semiconductor Manufacturing ## 1. The Core Exponential Model of Moore's Law ### 1.1 Fundamental Expression The foundational mathematical expression of Moore's Law describes transistor count as an exponential function of time: $$ N(t) = N_0 \cdot 2^{\frac{t}{T_d}} $$ **Variable Definitions:** - $N(t)$ — Transistor count at time $t$ - $N_0$ — Initial transistor count (reference point) - $T_d$ — Doubling period - Original (1965): $T_d \approx 12$ months - Revised (1975): $T_d \approx 24$ months ### 1.2 Continuous Form In continuous exponential form: $$ N(t) = N_0 \cdot e^{rt} $$ Where the continuous growth rate constant is: $$ r = \frac{\ln(2)}{T_d} $$ ### 1.3 Stepwise Exponential Model For modeling different technological phases: $$ T_i(t) = T_{i,0} \cdot e^{r_i(t - \tau_i)} $$ **Where:** - $T_i$ — Transistor density in phase $i$ - $r_i$ — Growth rate constant for phase $i$ - $\tau_i$ — Start time of phase $i$ **Doubling time calculation:** $$ t_2 = \frac{\ln(2)}{r_i} $$ ### 1.4 Key Historical Data Points | Year | Processor | Transistor Count | Process Node | |------|-----------|------------------|--------------| | 1971 | Intel 4004 | $2.3 \times 10^3$ | 10 µm | | 1989 | Intel 486 | $1.2 \times 10^6$ | 1 µm | | 2000 | Pentium 4 | $4.2 \times 10^7$ | 180 nm | | 2010 | Core i7 | $1.17 \times 10^9$ | 32 nm | | 2020 | Apple M1 | $1.6 \times 10^{10}$ | 5 nm | | 2025 | NVIDIA GB202 | $9.2 \times 10^{10}$ | 4 nm | ## 2. Dennard Scaling: The Power-Performance Equations ### 2.1 Fundamental Scaling Relationships For a scaling factor $S > 1$ (shrinking dimensions): **Dimensional Scaling:** $$ L \propto S^{-1}, \quad W \propto S^{-1}, \quad t_{ox} \propto S^{-1} $$ **Voltage and Threshold Scaling:** $$ V_{DD} \propto S^{-1}, \quad V_T \propto S^{-1} $$ **Doping Concentration (inverse scaling):** $$ N_A \propto S $$ ### 2.2 CMOS Power Model Total power consumption in CMOS circuits: $$ P_{total} = P_{dynamic} + P_{static} $$ **Dynamic Power:** $$ P_{dynamic} = \alpha \cdot C \cdot V_{DD}^2 \cdot f $$ **Where:** - $\alpha$ — Activity factor (switching probability) - $C$ — Load capacitance - $V_{DD}$ — Supply voltage - $f$ — Clock frequency **Static Power (Leakage):** $$ P_{static} = V_{DD} \cdot I_{leak} $$ **Complete Power Model:** $$ P = Q \cdot f \cdot C \cdot V^2 + V \cdot I_{leak} $$ Where $Q$ = number of transistors. ### 2.3 Dennard Scaling Predictions per Generation | Parameter | Symbol | Scaling Factor | Change | |-----------|--------|----------------|--------| | Linear dimensions | $L, W, t_{ox}$ | $0.7\times$ | −30% | | Device area | $A$ | $0.5\times$ | −50% | | Capacitance | $C$ | $0.7\times$ | −30% | | Voltage | $V_{DD}$ | $0.7\times$ | −30% | | Current | $I$ | $0.7\times$ | −30% | | Delay | $\tau$ | $0.7\times$ | −30% | | Frequency | $f$ | $1.4\times$ | +40% | | Power per transistor | $P/N$ | $0.5\times$ | −50% | | **Power density** | $P/A$ | $1.0\times$ | **Constant** | ### 2.4 Derived Relationships **Capacitance-Voltage-Frequency Relationship:** Since $C \propto \frac{\epsilon \cdot A}{t_{ox}}$ and both $A$ and $t_{ox}$ scale as $S^{-2}$ and $S^{-1}$ respectively: $$ C \propto S^{-1} $$ **Power Scaling:** $$ P = C \cdot V^2 \cdot f \propto S^{-1} \cdot S^{-2} \cdot S^{1} = S^{-2} $$ **Power Density:** $$ \frac{P}{A} \propto \frac{S^{-2}}{S^{-2}} = 1 \quad \text{(constant)} $$ ## 3. Lithography Resolution Limits: The Rayleigh Equation ### 3.1 Fundamental Resolution Criterion The Rayleigh criterion for optical lithography: $$ CD = k_1 \cdot \frac{\lambda}{NA} $$ **Variable Definitions:** - $CD$ — Critical dimension (minimum feature size) - $\lambda$ — Wavelength of light source - $NA$ — Numerical aperture of the optical system - $k_1$ — Process-dependent coefficient ($0.25 \leq k_1 \leq 1.0$) ### 3.2 Physical Limits **Theoretical minimum ($k_1 = 0.25$):** $$ CD_{min} = 0.25 \cdot \frac{\lambda}{NA} $$ **For 193nm immersion lithography ($NA_{max} = 1.35$):** $$ CD_{min} = 0.25 \cdot \frac{193 \text{ nm}}{1.35} \approx 36 \text{ nm} $$ **For EUV lithography ($\lambda = 13.5$ nm, $NA = 0.55$):** $$ CD_{min} = 0.25 \cdot \frac{13.5 \text{ nm}}{0.55} \approx 6.1 \text{ nm} $$ ### 3.3 Depth of Focus $$ DOF = k_2 \cdot \frac{\lambda}{NA^2} $$ **Where:** - $k_2$ — Process-dependent coefficient ($0.4 \leq k_2 \leq 1.0$) **Resolution-DOF Trade-off:** $$ CD \cdot DOF \propto \frac{\lambda^2}{NA^3} $$ ### 3.4 Half-Pitch Resolution For dense line/space patterns: $$ \text{Half-pitch}_{min} = \frac{k_1 \cdot \lambda}{NA} $$ **Abbe criterion (absolute limit):** $$ \text{Half-pitch}_{absolute} = \frac{0.25 \cdot \lambda}{NA} $$ ### 3.5 Lithography Technology Comparison | Technology | Wavelength ($\lambda$) | NA | $k_1$ (practical) | Min. Pitch | |------------|------------------------|-----|-------------------|------------| | i-line | 365 nm | 0.6 | 0.4 | 243 nm | | KrF DUV | 248 nm | 0.8 | 0.35 | 108 nm | | ArF DUV | 193 nm | 0.93 | 0.3 | 62 nm | | ArF Immersion | 193 nm | 1.35 | 0.28 | 40 nm | | EUV | 13.5 nm | 0.33 | 0.4 | 16 nm | | High-NA EUV | 13.5 nm | 0.55 | 0.35 | 8.6 nm | ## 4. Multi-Logistic Growth Model: Beyond Simple Exponentials ### 4.1 Limitations of Simple Exponential Empirical observations show: - Heteroscedasticity in transistor density data - Autocorrelation in residuals - Multiple inflection points in growth curves ### 4.2 Single Logistic Model $$ T(t) = \frac{K}{1 + e^{-r(t - \tau)}} $$ **Where:** - $K$ — Carrying capacity (saturation level) - $r$ — Intrinsic growth rate - $\tau$ — Time of inflection point (half-saturation) ### 4.3 Generalized Multi-Logistic Model For $n$ consecutive waves of technological development: $$ T(t) = \sum_{i=1}^{n} \frac{K_i}{1 + e^{-r_i(t - \tau_i)}} $$ **Parameters per phase $i$:** - $r_i$ — Intrinsic growth rate constant - $K_i$ — Saturation level for phase $i$ - $\tau_i$ — Characteristic time (midpoint) ### 4.4 Bi-Logistic Model (Observed in Intel Data) $$ T(t) = \frac{K_1}{1 + e^{-r_1(t - \tau_1)}} + \frac{K_2}{1 + e^{-r_2(t - \tau_2)}} $$ **Empirical findings:** - Phase 1 doubling time: $\approx 17$ months - Phase 2 doubling time: $\approx 33$ months - Characteristic times: $\tau \approx 9.5$ years per phase ### 4.5 Six-Wave Model Research identifies six distinct S-curves in transistor density evolution: $$ T(t) = \sum_{i=1}^{6} \frac{K_i}{1 + e^{-r_i(t - \tau_i)}} $$ **Pattern per wave:** - Rapid growth: ~6 years (10× density increase) - Plateau/consolidation: ~3 years - Transition to next wave ### 4.6 Growth Rate Dynamics The instantaneous growth rate: $$ \frac{dT}{dt} = r \cdot T \cdot \left(1 - \frac{T}{K}\right) $$ **Maximum growth rate occurs at:** $$ T^* = \frac{K}{2} \quad \text{(inflection point)} $$ ## 5. Wright's Law: Experience Curve Economics ### 5.1 Fundamental Relationship Cost as a function of cumulative production: $$ C(X) = C_0 \cdot X^{-\alpha} $$ **Where:** - $C(X)$ — Cost per unit at cumulative production $X$ - $C_0$ — Cost of first unit produced - $\alpha$ — Learning parameter (learning exponent) ### 5.2 Learning Rate The fractional cost reduction per doubling of cumulative production: $$ \text{Learning Rate} = 1 - 2^{-\alpha} $$ **Typical values for semiconductors:** - $\alpha \approx 0.2 - 0.35$ - Learning rate $\approx 13\% - 22\%$ ### 5.3 Log-Linear Form Taking logarithms: $$ \log C = \log C_0 - \alpha \cdot \log X $$ This produces a straight line on log-log axes. ### 5.4 Connection to Moore's Law When cumulative production grows exponentially: $$ X(t) = X_0 \cdot e^{gt} $$ Then: $$ C(t) = C_0 \cdot (X_0 \cdot e^{gt})^{-\alpha} = C_0 \cdot X_0^{-\alpha} \cdot e^{-\alpha g t} $$ **Key insight:** Wright's Law and Moore's Law produce equivalent forecasts when: $$ \log X \propto t \quad \text{(exponential production growth)} $$ ### 5.5 Price Decline Model For technologies following Wright's Law: $$ P(X) = P_0 \cdot \left(\frac{X}{X_0}\right)^{-\alpha} $$ **Example: Solar PV** - Learning rate: ~20% per doubling - $\alpha \approx 0.32$ ### 5.6 Semiconductor-Specific Learning **Cost per transistor decline:** $$ \frac{C}{N}(t) = \left(\frac{C}{N}\right)_0 \cdot e^{-\lambda t} $$ Where $\lambda$ captures combined effects of: - Increased transistor density - Manufacturing yield improvements - Process optimization ## 6. Rock's Law (Moore's Second Law): Fab Cost Escalation ### 6.1 Capital Cost Growth The cost of semiconductor fabrication facilities grows exponentially: $$ C_{fab}(t) = C_0 \cdot 2^{\frac{t}{T_{fab}}} $$ **Where:** - $C_{fab}(t)$ — Fab cost at time $t$ - $C_0$ — Reference fab cost - $T_{fab} \approx 4$ years (doubling period) ### 6.2 Continuous Form $$ C_{fab}(t) = C_0 \cdot e^{r_{fab} \cdot t} $$ Where: $$ r_{fab} = \frac{\ln(2)}{T_{fab}} \approx 0.173 \text{ per year} $$ ### 6.3 Equipment Cost Scaling Lithography tool cost escalation: $$ C_{litho}(n) = C_{litho,0} \cdot 2^{n/2} $$ Where $n$ = number of technology nodes advanced. **Example costs (2024):** - ArF immersion scanner: ~$100M - EUV scanner: ~$200M - High-NA EUV scanner: ~$400M ### 6.4 Economic Sustainability Condition For continued scaling, cost reduction must outpace fab cost increase: $$ \frac{d}{dt}\left(\frac{C_{fab}}{N \cdot Y}\right) < 0 $$ Where: - $N$ — Transistors per chip - $Y$ — Manufacturing yield This requires: $$ \frac{d N}{dt} + \frac{d Y}{dt} > \frac{d C_{fab}}{dt} $$ ## 7. Quantum Tunneling Limits: The Physical Boundary ### 7.1 Tunneling Probability For a rectangular potential barrier: $$ T \approx \exp\left(-2\kappa d\right) $$ **Where the decay constant:** $$ \kappa = \frac{\sqrt{2m^*(U - E)}}{\hbar} $$ **Variables:** - $d$ — Barrier thickness - $U$ — Barrier height (potential energy) - $E$ — Electron kinetic energy - $m^*$ — Effective electron mass - $\hbar$ — Reduced Planck constant ### 7.2 WKB Approximation For arbitrary barrier shapes $U(x)$: $$ T \approx \exp\left(-\frac{2}{\hbar}\int_{x_1}^{x_2}\sqrt{2m^*(U(x) - E)} \, dx\right) $$ ### 7.3 Gate Oxide Tunneling Current Direct tunneling current density through gate oxide: $$ J_g = A \cdot E_{ox}^2 \cdot \exp\left(-\frac{B}{E_{ox}}\right) $$ **Where:** $$ B = \frac{4\sqrt{2m^*}\phi_B^{3/2}}{3q\hbar} $$ **Variables:** - $E_{ox}$ — Electric field across oxide - $\phi_B$ — Barrier height - $m^*$ — Effective mass in oxide - $q$ — Electron charge ### 7.4 Fowler-Nordheim Tunneling For thicker oxides under high fields: $$ J_{FN} = \frac{q^3 E_{ox}^2}{16\pi^2\hbar\phi_B} \cdot \exp\left(-\frac{4\sqrt{2m^*}\phi_B^{3/2}}{3q\hbar E_{ox}}\right) $$ ### 7.5 Subthreshold Swing Limit Thermal limit on switching steepness: $$ SS_{min} = \frac{kT}{q} \cdot \ln(10) \approx 60 \text{ mV/decade} \quad \text{(at 300K)} $$ **Temperature dependence:** $$ SS_{min}(T) = \frac{kT \cdot \ln(10)}{q} = 2.3 \cdot \frac{kT}{q} $$ ### 7.6 Physical Size Limits **Gate oxide thickness limit:** $$ t_{ox,min} \approx 1 \text{ nm} $$ **Channel length limit (conventional MOSFET):** $$ L_{ch,min} \approx 1-3 \text{ nm} $$ **Limiting factors:** - Direct source-drain tunneling - Gate oxide tunneling - Quantum confinement effects - Statistical dopant fluctuation ### 7.7 Source-Drain Tunneling Leakage current due to direct tunneling: $$ I_{SD,tunnel} \propto \exp\left(-\frac{2L_{ch}}{\lambda}\right) $$ Where $\lambda$ is the characteristic tunneling length: $$ \lambda = \frac{\hbar}{\sqrt{2m^*E_g}} $$ ## 8. The Breakdown of Dennard Scaling (Post-2006) ### 8.1 Voltage Scaling Limit Threshold voltage cannot scale below: $$ V_T > \frac{kT}{q} \cdot \ln\left(\frac{I_{on}}{I_{off}}\right) \cdot \frac{1}{n} $$ **Where:** - $n$ — Subthreshold ideality factor (~1.0-1.5) - $I_{on}/I_{off}$ — Required on/off current ratio (~$10^6$) **Practical minimum:** $$ V_T \gtrsim 0.2-0.3 \text{ V} $$ ### 8.2 Leakage Current Growth Subthreshold leakage scales exponentially with $V_T$: $$ I_{off} \propto \exp\left(-\frac{qV_T}{nkT}\right) $$ As $V_T$ decreases, leakage increases exponentially. ### 8.3 Post-Dennard Power Density After Dennard scaling breakdown (~65nm node, ~2006): $$ \frac{P}{A} \propto S^{\beta} \quad \text{where } \beta \approx 0.5 - 1.0 $$ **Power density increase per generation:** $$ \Delta\left(\frac{P}{A}\right) \approx 1.2\times - 1.5\times $$ ### 8.4 Dark Silicon Fraction of chip that can be active simultaneously: $$ f_{active} = \frac{P_{budget}}{P_{density} \cdot A_{chip}} $$ As power density increases, $f_{active}$ decreases: $$ f_{active}(n) \approx f_0 \cdot S^{-\beta n} $$ Where $n$ = number of generations past Dennard breakdown. ### 8.5 Utilization Wall Maximum useful transistor utilization: $$ U_{max} = \frac{P_{TDP}}{P_{transistor} \cdot N} $$ **Trend:** $$ U_{max}(t) \propto 2^{-t/T_U} $$ Where $T_U \approx 2-3$ years. ## 9. Koomey's Law: Energy Efficiency Scaling ### 9.1 Performance per Watt Computations per joule of energy: $$ \eta(t) = \eta_0 \cdot 2^{\frac{t}{T_K}} $$ **Historical doubling period:** $$ T_K \approx 1.5 \text{ years} $$ ### 9.2 Derivation from Moore + Dennard During Dennard era: - Transistor count: $N \propto 2^{t/2}$ (Moore, 2-year doubling) - Power constant: $P = \text{const}$ (Dennard) - Performance $\propto N$ Therefore: $$ \frac{\text{Performance}}{P} \propto 2^{t/2} $$ With frequency scaling ($f \propto 1.4^{t/2}$): $$ \frac{\text{Computations}}{J} \propto 2^{t/1.5} $$ ### 9.3 Post-Dennard Koomey Scaling After 2006, efficiency gains slow: $$ T_K \approx 2.5 - 3 \text{ years} $$ ### 9.4 Energy per Operation $$ E_{op}(t) = E_0 \cdot 2^{-t/T_K} $$ **Minimum energy per bit operation (Landauer limit):** $$ E_{min} = kT \cdot \ln(2) \approx 2.9 \times 10^{-21} \text{ J} \quad \text{(at 300K)} $$ ## 10. Integrated Economic Model ### 10.1 Cost per Transistor $$ \frac{C_{chip}}{N} = \frac{C_{wafer}}{Y \cdot A_{die} \cdot \rho} $$ **Where:** - $C_{wafer}$ — Wafer processing cost - $Y$ — Yield (fraction of good dice) - $A_{die}$ — Die area - $\rho$ — Transistor density (transistors/mm²) ### 10.2 Yield Models **Poisson (defect-limited) model:** $$ Y = e^{-D_0 \cdot A_{die}} $$ **Murphy's model:** $$ Y = \left(\frac{1 - e^{-D_0 \cdot A_{die}}}{D_0 \cdot A_{die}}\right)^2 $$ **Seeds' model:** $$ Y = e^{-\sqrt{D_0 \cdot A_{die}}} $$ ### 10.3 Learning Curve Yield Model Yield improvement with cumulative production: $$ Y(X) = Y_{\infty} - (Y_{\infty} - Y_0) \cdot e^{-\gamma X} $$ **Or power law form:** $$ Y(X) = Y_0 \cdot X^{\beta} $$ ### 10.4 Die Cost Model $$ C_{die} = \frac{C_{wafer}}{\pi \cdot (D/2)^2 / A_{die} \cdot Y} $$ Where $D$ = wafer diameter. **Usable dice per wafer (approximate):** $$ N_{dice} \approx \frac{\pi D^2}{4 A_{die}} - \frac{\pi D}{\sqrt{2 A_{die}}} $$ ### 10.5 Cost per Function (Moore's Original Metric) $$ C_f(n) = C_{f,0} \cdot 2^{-n} $$ Where $n$ = number of Moore's Law generations. **Moore's condition for sustainable scaling:** $$ \frac{\Delta C_f}{C_f} \leq -30\% \text{ per transistor doubling} $$ ### 10.6 Total Cost of Ownership $$ TCO = C_{fab} + C_{equipment} + C_{materials} + C_{labor} + C_{yield\_loss} $$ **Normalized per transistor:** $$ \frac{TCO}{N_{total}} = \frac{C_{fab}/L_{fab} + C_{wafer} \cdot W_{annual}}{N_{die} \cdot D_{annual} \cdot Y} $$ Where: - $L_{fab}$ — Fab lifetime (years) - $W_{annual}$ — Annual wafer starts - $D_{annual}$ — Annual die output ## 11. The Mathematical Ecosystem ### 11.1 Interconnected Relationships ``` - ┌─────────────────────────────────────────────────────────────┐ │ MOORE'S LAW │ │ N(t) = N₀ \cdot 2^(t/Td) │ │ (Exponential transistor growth) │ └─────────────────────┬───────────────────────────────────────┘ │ ▼ ┌─────────────────────────────────────────────────────────────┐ │ DENNARD SCALING │ │ P/A = constant (ideal) │ │ [BROKEN c. 2006 at ~65nm node] │ └─────────────────────┬───────────────────────────────────────┘ │ ▼ ┌─────────────────────────────────────────────────────────────┐ │ LITHOGRAPHY LIMITS │ │ CD = k₁ \cdot λ/NA │ │ (Rayleigh criterion, k₁ ≥ 0.25) │ └─────────────────────┬───────────────────────────────────────┘ │ ▼ ┌─────────────────────────────────────────────────────────────┐ │ QUANTUM LIMITS │ │ T ∝ exp(-2κd), tunneling │ │ (Physical limit ~1-3 nm) │ └─────────────────────┬───────────────────────────────────────┘ │ ▼ ┌─────────────────────────────────────────────────────────────┐ │ ECONOMIC CONSTRAINTS │ │ Rock's Law: C_fab ∝ 2^(t/4) │ │ Wright's Law: C ∝ X^(-α) │ └─────────────────────────────────────────────────────────────┘ ``` ### 11.2 Equations | Law/Model | Equation | Domain | |-----------|----------|--------| | Moore's Law | $N(t) = N_0 \cdot 2^{t/T_d}$ | Transistor count | | Dennard Scaling | $P/A = \text{const}$ | Power density | | Rayleigh Criterion | $CD = k_1 \lambda / NA$ | Lithography | | Tunneling | $T \sim e^{-2\kappa d}$ | Quantum limit | | Wright's Law | $C = C_0 X^{-\alpha}$ | Learning curve | | Rock's Law | $C_{fab} = C_0 \cdot 2^{t/4}$ | Fab cost | | Koomey's Law | $\eta = \eta_0 \cdot 2^{t/1.5}$ | Efficiency | ### 11.3 Current State (2025) **Transition from 1D to multi-dimensional scaling:** $$ \text{Performance} = f(\text{density}, \text{architecture}, \text{packaging}, \text{software}) $$ **"More than Moore" approach:** $$ \text{Value} \neq \text{Transistor Count} $$ Instead: $$ \text{Value} = \int \text{(Functionality × Efficiency × Integration)} \, d(\text{innovation}) $$ ## Physical Constants | Constant | Symbol | Value | |----------|--------|-------| | Boltzmann constant | $k$ | $1.381 \times 10^{-23}$ J/K | | Elementary charge | $q$ | $1.602 \times 10^{-19}$ C | | Planck constant | $h$ | $6.626 \times 10^{-34}$ J\cdots | | Reduced Planck | $\hbar$ | $1.055 \times 10^{-34}$ J\cdots | | Electron mass | $m_e$ | $9.109 \times 10^{-31}$ kg | | Thermal voltage (300K) | $kT/q$ | 25.9 mV | ## Technology Node Progression | Node Name | Year | Gate Length | Density (MTr/mm²) | |-----------|------|-------------|-------------------| | 180 nm | 1999 | 130 nm | 1.7 | | 130 nm | 2001 | 90 nm | 3.3 | | 90 nm | 2003 | 50 nm | 6.5 | | 65 nm | 2005 | 35 nm | 13 | | 45 nm | 2007 | 25 nm | 26 | | 32 nm | 2009 | 20 nm | 52 | | 22 nm | 2012 | 14 nm | 100 | | 14 nm | 2014 | 10 nm | 170 | | 10 nm | 2016 | 7 nm | 280 | | 7 nm | 2018 | 5 nm | 450 | | 5 nm | 2020 | 3.5 nm | 700 | | 3 nm | 2022 | 2.5 nm | 1100 | | 2 nm | 2025 | 1.8 nm | 1700 |
# Semiconductor Economics: Chip, Wafer, and Fab Costs ## Overview Semiconductor economics operates across three interconnected cost levels, each driving the next in a hierarchical structure that determines the final price of every chip. ## 1. Fab (Fabrication Plant) Cost The foundation of semiconductor economics—the capital expenditure required to build and equip a fabrication facility. ### Capital Expenditure Breakdown - **Modern leading-edge fabs (3nm/2nm):** $15–25+ billion to construct - **Historical comparison:** - Year 2000: ~$1–2 billion per fab - Year 2010: ~$3–5 billion per fab - Year 2020: ~$10–15 billion per fab - Year 2024+: ~$20–30 billion per fab ### Cost Components - **Equipment (70–80% of capital cost):** - ASML EUV lithography machines: ~$350–400 million each - Deposition tools (CVD, PVD): $5–20 million each - Etching systems: $5–15 million each - Metrology and inspection: $2–10 million each - Ion implantation: $3–8 million each - **Facility construction (20–30% of capital cost):** - Cleanroom (Class 1-10): $3,000–5,000 per square foot - Ultra-pure water systems: $100–500 million - Vibration isolation foundations - Chemical delivery systems - HVAC and air filtration ### Depreciation Model Fab equipment is typically depreciated over 5–7 years: $$ \text{Annual Depreciation} = \frac{\text{Fab Capital Cost}}{\text{Depreciation Period}} $$ **Example:** $$ \text{Annual Depreciation} = \frac{\$20 \text{ billion}}{5 \text{ years}} = \$4 \text{ billion/year} $$ ## 2. Wafer Cost The cost to process a single silicon wafer (typically 300mm diameter) through hundreds of manufacturing steps. ### Wafer Cost by Process Node | Node | Approximate Wafer Cost | Typical Applications | |------|------------------------|---------------------| | 3nm | $18,000–$22,000 | Flagship mobile SoCs, high-end GPUs | | 5nm | $16,000–$18,000 | Premium smartphones, AI accelerators | | 7nm | $10,000–$12,000 | Gaming consoles, data center CPUs | | 14nm | $5,000–$7,000 | Mid-range processors, FPGAs | | 28nm | $3,000–$4,000 | Automotive, WiFi, Bluetooth | | 65nm | $2,000–$2,500 | MCUs, power management | | 180nm | $1,000–$1,500 | Analog, sensors, legacy | ### Wafer Cost Formula $$ C_{\text{wafer}} = C_{\text{depreciation}} + C_{\text{materials}} + C_{\text{labor}} + C_{\text{utilities}} + C_{\text{overhead}} $$ Where: - $C_{\text{depreciation}}$ = Equipment depreciation per wafer - $C_{\text{materials}}$ = Silicon, photoresists, gases, chemicals, CMP slurries - $C_{\text{labor}}$ = Engineering and technician costs - $C_{\text{utilities}}$ = Electricity, ultra-pure water, gases - $C_{\text{overhead}}$ = Maintenance, yield engineering, facility costs ### Wafer Throughput Economics $$ C_{\text{depreciation/wafer}} = \frac{\text{Annual Depreciation}}{\text{Wafers per Year}} $$ **Example for a $20B fab producing 100,000 wafers/month:** $$ C_{\text{depreciation/wafer}} = \frac{\$4 \text{ billion/year}}{1.2 \text{ million wafers/year}} \approx \$3,333 \text{ per wafer} $$ ## 3. Chip Die Cost The cost per individual chip, derived from wafer economics and manufacturing yield. ### Fundamental Die Cost Equation $$ C_{\text{die}} = \frac{C_{\text{wafer}}}{N_{\text{dies}} \times Y} $$ Where: - $C_{\text{die}}$ = Cost per good die - $C_{\text{wafer}}$ = Total wafer processing cost - $N_{\text{dies}}$ = Number of dies per wafer (gross) - $Y$ = Yield (fraction of functional dies) ### Dies Per Wafer Calculation For a circular wafer with rectangular dies: $$ N_{\text{dies}} \approx \frac{\pi \times D^2}{4 \times A_{\text{die}}} - \frac{\pi \times D}{\sqrt{2 \times A_{\text{die}}}} $$ Where: - $D$ = Wafer diameter (300mm for modern fabs) - $A_{\text{die}}$ = Die area in mm² **Simplified approximation:** $$ N_{\text{dies}} \approx \frac{\pi \times (150)^2}{A_{\text{die}}} \times 0.85 $$ The 0.85 factor accounts for edge losses and scribe lines. ### Dies Per Wafer Examples | Die Size (mm²) | Approximate Dies/Wafer | Example Chips | |----------------|------------------------|---------------| | 5 | ~12,000 | Small MCUs, sensors | | 25 | ~2,400 | Bluetooth, WiFi chips | | 100 | ~600 | Mobile SoCs, mid-range GPUs | | 300 | ~200 | Desktop CPUs, gaming GPUs | | 600 | ~90 | Data center GPUs | | 800 | ~60 | Large AI accelerators (H100) | | 1,200 | ~35 | Largest monolithic dies | ### Yield Models #### Murphy's Yield Model $$ Y = \left( \frac{1 - e^{-D_0 \times A}}{D_0 \times A} \right)^2 $$ #### Poisson Yield Model (simpler) $$ Y = e^{-D_0 \times A} $$ Where: - $Y$ = Die yield (fraction) - $D_0$ = Defect density (defects per cm²) - $A$ = Die area (cm²) **Typical defect densities:** - Mature process: $D_0 \approx 0.05–0.1$ defects/cm² - New process (early): $D_0 \approx 0.3–0.5$ defects/cm² - New process (ramping): $D_0 \approx 0.1–0.2$ defects/cm² ### Yield Impact For a 600mm² die ($A = 6$ cm²): **Mature process** ($D_0 = 0.1$): $$ Y = e^{-0.1 \times 6} = e^{-0.6} \approx 0.55 = 55\% $$ **Early production** ($D_0 = 0.3$): $$ Y = e^{-0.3 \times 6} = e^{-1.8} \approx 0.17 = 17\% $$ ## 4. Cost Model ### Total Manufacturing Cost Per Chip $$ C_{\text{total}} = C_{\text{die}} + C_{\text{packaging}} + C_{\text{testing}} + C_{\text{design\_amort}} $$ Where: $$ C_{\text{design\_amort}} = \frac{C_{\text{NRE}}}{\text{Total Units Produced}} $$ - $C_{\text{NRE}}$ = Non-Recurring Engineering costs (design, masks, validation) ### NRE Costs by Node | Node | Approximate NRE Cost | |------|---------------------| | 3nm | $500M – $1B+ | | 5nm | $400M – $700M | | 7nm | $250M – $400M | | 14nm | $100M – $200M | | 28nm | $50M – $100M | | 65nm | $20M – $40M | ### Packaging Costs - **Standard wire bond:** $0.10 – $1.00 - **Flip chip BGA:** $2 – $10 - **Advanced fan-out (InFO):** $10 – $50 - **2.5D interposer (CoWoS):** $100 – $400 - **3D stacking:** $200 – $600+ ## 5. Examples ### Example 1: AI Accelerator Chip **Parameters:** - Node: TSMC 5nm - Die size: 600mm² - Wafer cost: $17,000 - Defect density: $D_0 = 0.12$ /cm² **Calculations:** **Dies per wafer:** $$ N_{\text{dies}} = \frac{\pi \times 150^2}{600} \times 0.85 \approx 100 \text{ dies} $$ **Yield:** $$ Y = e^{-0.12 \times 6} \approx e^{-0.72} \approx 0.49 = 49\% $$ **Die cost:** $$ C_{\text{die}} = \frac{\$17,000}{100 \times 0.49} = \frac{\$17,000}{49} \approx \$347 $$ **Total chip cost:** $$ C_{\text{total}} = \$347 + \$250_{\text{(CoWoS)}} + \$30_{\text{(test)}} + \$50_{\text{(design)}} \approx \$677 $$ ### Example 2: IoT Microcontroller **Parameters:** - Node: 40nm - Die size: 5mm² - Wafer cost: $3,000 - Defect density: $D_0 = 0.05$ /cm² **Calculations:** **Dies per wafer:** $$ N_{\text{dies}} = \frac{\pi \times 150^2}{5} \times 0.85 \approx 12,000 \text{ dies} $$ **Yield:** $$ Y = e^{-0.05 \times 0.05} \approx e^{-0.0025} \approx 0.997 = 99.7\% $$ **Die cost:** $$ C_{\text{die}} = \frac{\$3,000}{12,000 \times 0.997} \approx \$0.25 $$ **Total chip cost:** $$ C_{\text{total}} = \$0.25 + \$0.15_{\text{(pkg)}} + \$0.05_{\text{(test)}} + \$0.05_{\text{(design)}} \approx \$0.50 $$ ## 6. Economic Dynamics ### Learning Curve Effect Manufacturing cost decreases with cumulative volume: $$ C_n = C_1 \times n^{-b} $$ Where: - $C_n$ = Cost at cumulative unit $n$ - $C_1$ = Cost of first unit - $b$ = Learning exponent (typically 0.1–0.3 for semiconductors) - Learning rate = $2^{-b}$ (typically 85–95%) ### Economies of Scale **Fab utilization impact:** $$ C_{\text{wafer}}(\text{util}) = \frac{C_{\text{fixed}}}{\text{util}} + C_{\text{variable}} $$ - At 50% utilization: costs ~1.5× baseline - At 90% utilization: costs ~1.05× baseline - At 100% utilization: minimum cost achieved ### Cost Sensitivity Analysis **Die cost sensitivity to yield:** $$ \frac{\partial C_{\text{die}}}{\partial Y} = -\frac{C_{\text{wafer}}}{N_{\text{dies}} \times Y^2} $$ For large, expensive dies, yield improvements have dramatic cost impacts. ## 7. Industry Structure Implications ### Why Only 3 Companies at Leading Edge **Minimum efficient scale calculation:** $$ \text{Revenue Required} = \frac{\text{Annual CapEx} + \text{R\&D}}{\text{Margin}} $$ $$ \text{Revenue Required} \approx \frac{\$15B + \$5B}{0.40} = \$50B+ \text{ annually} $$ Only TSMC, Samsung, and Intel can sustain this investment level. ### Foundry Model Economics **Fabless company advantage:** $$ \text{ROI}_{\text{fabless}} = \frac{\text{Chip Revenue} - \text{Foundry Cost} - \text{Design Cost}}{\text{Design Cost}} $$ **IDM (Integrated Device Manufacturer):** $$ \text{ROI}_{\text{IDM}} = \frac{\text{Chip Revenue} - \text{Mfg Cost} - \text{Design Cost}}{\text{Fab CapEx} + \text{Design Cost}} $$ The fabless model eliminates fab capital from the denominator, enabling higher ROI for design-focused companies. ## 8. Equations ### Core Formulas Reference | Metric | Formula | |--------|---------| | Die Cost | $C_{\text{die}} = \frac{C_{\text{wafer}}}{N_{\text{dies}} \times Y}$ | | Dies per Wafer | $N \approx \frac{\pi r^2}{A_{\text{die}}} \times 0.85$ | | Poisson Yield | $Y = e^{-D_0 \times A}$ | | Total Cost | $C_{\text{total}} = C_{\text{die}} + C_{\text{pkg}} + C_{\text{test}} + C_{\text{NRE}}$ | | Depreciation/Wafer | $C_{\text{dep}} = \frac{\text{CapEx}/t}{\text{WPY}}$ | | Learning Curve | $C_n = C_1 \times n^{-b}$ | ## 9. Market Dynamics ### Key Trends - **AI demand:** Consuming 20%+ of advanced node capacity - **Geopolitical reshoring:** Adding 20–30% cost premium for non-Taiwan fabs - **EUV bottleneck:** ASML's monopoly constrains expansion - **Advanced packaging:** Becoming equal cost driver to node shrinks - **Chiplet economics:** Enabling yield improvement through smaller dies ### Government Subsidies Impact - **US CHIPS Act:** $52B in subsidies - **EU Chips Act:** €43B in public/private investment - **Effect:** Artificially reducing effective CapEx for new fabs
# Semiconductor Economics: Chip, Wafer, and Fab Costs ## Overview Semiconductor economics operates across three interconnected cost levels, each driving the next in a hierarchical structure that determines the final price of every chip. ## 1. Fab (Fabrication Plant) Cost The foundation of semiconductor economics—the capital expenditure required to build and equip a fabrication facility. ### Capital Expenditure Breakdown - **Modern leading-edge fabs (3nm/2nm):** $15–25+ billion to construct - **Historical comparison:** - Year 2000: ~$1–2 billion per fab - Year 2010: ~$3–5 billion per fab - Year 2020: ~$10–15 billion per fab - Year 2024+: ~$20–30 billion per fab ### Cost Components - **Equipment (70–80% of capital cost):** - ASML EUV lithography machines: ~$350–400 million each - Deposition tools (CVD, PVD): $5–20 million each - Etching systems: $5–15 million each - Metrology and inspection: $2–10 million each - Ion implantation: $3–8 million each - **Facility construction (20–30% of capital cost):** - Cleanroom (Class 1-10): $3,000–5,000 per square foot - Ultra-pure water systems: $100–500 million - Vibration isolation foundations - Chemical delivery systems - HVAC and air filtration ### Depreciation Model Fab equipment is typically depreciated over 5–7 years: $$ \text{Annual Depreciation} = \frac{\text{Fab Capital Cost}}{\text{Depreciation Period}} $$ **Example:** $$ \text{Annual Depreciation} = \frac{\$20 \text{ billion}}{5 \text{ years}} = \$4 \text{ billion/year} $$ ## 2. Wafer Cost The cost to process a single silicon wafer (typically 300mm diameter) through hundreds of manufacturing steps. ### Wafer Cost by Process Node | Node | Approximate Wafer Cost | Typical Applications | |------|------------------------|---------------------| | 3nm | $18,000–$22,000 | Flagship mobile SoCs, high-end GPUs | | 5nm | $16,000–$18,000 | Premium smartphones, AI accelerators | | 7nm | $10,000–$12,000 | Gaming consoles, data center CPUs | | 14nm | $5,000–$7,000 | Mid-range processors, FPGAs | | 28nm | $3,000–$4,000 | Automotive, WiFi, Bluetooth | | 65nm | $2,000–$2,500 | MCUs, power management | | 180nm | $1,000–$1,500 | Analog, sensors, legacy | ### Wafer Cost Formula $$ C_{\text{wafer}} = C_{\text{depreciation}} + C_{\text{materials}} + C_{\text{labor}} + C_{\text{utilities}} + C_{\text{overhead}} $$ Where: - $C_{\text{depreciation}}$ = Equipment depreciation per wafer - $C_{\text{materials}}$ = Silicon, photoresists, gases, chemicals, CMP slurries - $C_{\text{labor}}$ = Engineering and technician costs - $C_{\text{utilities}}$ = Electricity, ultra-pure water, gases - $C_{\text{overhead}}$ = Maintenance, yield engineering, facility costs ### Wafer Throughput Economics $$ C_{\text{depreciation/wafer}} = \frac{\text{Annual Depreciation}}{\text{Wafers per Year}} $$ **Example for a $20B fab producing 100,000 wafers/month:** $$ C_{\text{depreciation/wafer}} = \frac{\$4 \text{ billion/year}}{1.2 \text{ million wafers/year}} \approx \$3,333 \text{ per wafer} $$ ## 3. Chip Die Cost The cost per individual chip, derived from wafer economics and manufacturing yield. ### Fundamental Die Cost Equation $$ C_{\text{die}} = \frac{C_{\text{wafer}}}{N_{\text{dies}} \times Y} $$ Where: - $C_{\text{die}}$ = Cost per good die - $C_{\text{wafer}}$ = Total wafer processing cost - $N_{\text{dies}}$ = Number of dies per wafer (gross) - $Y$ = Yield (fraction of functional dies) ### Dies Per Wafer Calculation For a circular wafer with rectangular dies: $$ N_{\text{dies}} \approx \frac{\pi \times D^2}{4 \times A_{\text{die}}} - \frac{\pi \times D}{\sqrt{2 \times A_{\text{die}}}} $$ Where: - $D$ = Wafer diameter (300mm for modern fabs) - $A_{\text{die}}$ = Die area in mm² **Simplified approximation:** $$ N_{\text{dies}} \approx \frac{\pi \times (150)^2}{A_{\text{die}}} \times 0.85 $$ The 0.85 factor accounts for edge losses and scribe lines. ### Dies Per Wafer Examples | Die Size (mm²) | Approximate Dies/Wafer | Example Chips | |----------------|------------------------|---------------| | 5 | ~12,000 | Small MCUs, sensors | | 25 | ~2,400 | Bluetooth, WiFi chips | | 100 | ~600 | Mobile SoCs, mid-range GPUs | | 300 | ~200 | Desktop CPUs, gaming GPUs | | 600 | ~90 | Data center GPUs | | 800 | ~60 | Large AI accelerators (H100) | | 1,200 | ~35 | Largest monolithic dies | ### Yield Models #### Murphy's Yield Model $$ Y = \left( \frac{1 - e^{-D_0 \times A}}{D_0 \times A} \right)^2 $$ #### Poisson Yield Model (simpler) $$ Y = e^{-D_0 \times A} $$ Where: - $Y$ = Die yield (fraction) - $D_0$ = Defect density (defects per cm²) - $A$ = Die area (cm²) **Typical defect densities:** - Mature process: $D_0 \approx 0.05–0.1$ defects/cm² - New process (early): $D_0 \approx 0.3–0.5$ defects/cm² - New process (ramping): $D_0 \approx 0.1–0.2$ defects/cm² ### Yield Impact For a 600mm² die ($A = 6$ cm²): **Mature process** ($D_0 = 0.1$): $$ Y = e^{-0.1 \times 6} = e^{-0.6} \approx 0.55 = 55\% $$ **Early production** ($D_0 = 0.3$): $$ Y = e^{-0.3 \times 6} = e^{-1.8} \approx 0.17 = 17\% $$ ## 4. Cost Model ### Total Manufacturing Cost Per Chip $$ C_{\text{total}} = C_{\text{die}} + C_{\text{packaging}} + C_{\text{testing}} + C_{\text{design\_amort}} $$ Where: $$ C_{\text{design\_amort}} = \frac{C_{\text{NRE}}}{\text{Total Units Produced}} $$ - $C_{\text{NRE}}$ = Non-Recurring Engineering costs (design, masks, validation) ### NRE Costs by Node | Node | Approximate NRE Cost | |------|---------------------| | 3nm | $500M – $1B+ | | 5nm | $400M – $700M | | 7nm | $250M – $400M | | 14nm | $100M – $200M | | 28nm | $50M – $100M | | 65nm | $20M – $40M | ### Packaging Costs - **Standard wire bond:** $0.10 – $1.00 - **Flip chip BGA:** $2 – $10 - **Advanced fan-out (InFO):** $10 – $50 - **2.5D interposer (CoWoS):** $100 – $400 - **3D stacking:** $200 – $600+ ## 5. Examples ### Example 1: AI Accelerator Chip **Parameters:** - Node: TSMC 5nm - Die size: 600mm² - Wafer cost: $17,000 - Defect density: $D_0 = 0.12$ /cm² **Calculations:** **Dies per wafer:** $$ N_{\text{dies}} = \frac{\pi \times 150^2}{600} \times 0.85 \approx 100 \text{ dies} $$ **Yield:** $$ Y = e^{-0.12 \times 6} \approx e^{-0.72} \approx 0.49 = 49\% $$ **Die cost:** $$ C_{\text{die}} = \frac{\$17,000}{100 \times 0.49} = \frac{\$17,000}{49} \approx \$347 $$ **Total chip cost:** $$ C_{\text{total}} = \$347 + \$250_{\text{(CoWoS)}} + \$30_{\text{(test)}} + \$50_{\text{(design)}} \approx \$677 $$ ### Example 2: IoT Microcontroller **Parameters:** - Node: 40nm - Die size: 5mm² - Wafer cost: $3,000 - Defect density: $D_0 = 0.05$ /cm² **Calculations:** **Dies per wafer:** $$ N_{\text{dies}} = \frac{\pi \times 150^2}{5} \times 0.85 \approx 12,000 \text{ dies} $$ **Yield:** $$ Y = e^{-0.05 \times 0.05} \approx e^{-0.0025} \approx 0.997 = 99.7\% $$ **Die cost:** $$ C_{\text{die}} = \frac{\$3,000}{12,000 \times 0.997} \approx \$0.25 $$ **Total chip cost:** $$ C_{\text{total}} = \$0.25 + \$0.15_{\text{(pkg)}} + \$0.05_{\text{(test)}} + \$0.05_{\text{(design)}} \approx \$0.50 $$ ## 6. Economic Dynamics ### Learning Curve Effect Manufacturing cost decreases with cumulative volume: $$ C_n = C_1 \times n^{-b} $$ Where: - $C_n$ = Cost at cumulative unit $n$ - $C_1$ = Cost of first unit - $b$ = Learning exponent (typically 0.1–0.3 for semiconductors) - Learning rate = $2^{-b}$ (typically 85–95%) ### Economies of Scale **Fab utilization impact:** $$ C_{\text{wafer}}(\text{util}) = \frac{C_{\text{fixed}}}{\text{util}} + C_{\text{variable}} $$ - At 50% utilization: costs ~1.5× baseline - At 90% utilization: costs ~1.05× baseline - At 100% utilization: minimum cost achieved ### Cost Sensitivity Analysis **Die cost sensitivity to yield:** $$ \frac{\partial C_{\text{die}}}{\partial Y} = -\frac{C_{\text{wafer}}}{N_{\text{dies}} \times Y^2} $$ For large, expensive dies, yield improvements have dramatic cost impacts. ## 7. Industry Structure Implications ### Why Only 3 Companies at Leading Edge **Minimum efficient scale calculation:** $$ \text{Revenue Required} = \frac{\text{Annual CapEx} + \text{R\&D}}{\text{Margin}} $$ $$ \text{Revenue Required} \approx \frac{\$15B + \$5B}{0.40} = \$50B+ \text{ annually} $$ Only TSMC, Samsung, and Intel can sustain this investment level. ### Foundry Model Economics **Fabless company advantage:** $$ \text{ROI}_{\text{fabless}} = \frac{\text{Chip Revenue} - \text{Foundry Cost} - \text{Design Cost}}{\text{Design Cost}} $$ **IDM (Integrated Device Manufacturer):** $$ \text{ROI}_{\text{IDM}} = \frac{\text{Chip Revenue} - \text{Mfg Cost} - \text{Design Cost}}{\text{Fab CapEx} + \text{Design Cost}} $$ The fabless model eliminates fab capital from the denominator, enabling higher ROI for design-focused companies. ## 8. Equations ### Core Formulas Reference | Metric | Formula | |--------|---------| | Die Cost | $C_{\text{die}} = \frac{C_{\text{wafer}}}{N_{\text{dies}} \times Y}$ | | Dies per Wafer | $N \approx \frac{\pi r^2}{A_{\text{die}}} \times 0.85$ | | Poisson Yield | $Y = e^{-D_0 \times A}$ | | Total Cost | $C_{\text{total}} = C_{\text{die}} + C_{\text{pkg}} + C_{\text{test}} + C_{\text{NRE}}$ | | Depreciation/Wafer | $C_{\text{dep}} = \frac{\text{CapEx}/t}{\text{WPY}}$ | | Learning Curve | $C_n = C_1 \times n^{-b}$ | ## 9. Market Dynamics ### Key Trends - **AI demand:** Consuming 20%+ of advanced node capacity - **Geopolitical reshoring:** Adding 20–30% cost premium for non-Taiwan fabs - **EUV bottleneck:** ASML's monopoly constrains expansion - **Advanced packaging:** Becoming equal cost driver to node shrinks - **Chiplet economics:** Enabling yield improvement through smaller dies ### Government Subsidies Impact - **US CHIPS Act:** $52B in subsidies - **EU Chips Act:** €43B in public/private investment - **Effect:** Artificially reducing effective CapEx for new fabs
# Chip Packaging ## Mathematical Modeling Mathematical frameworks used in chip packaging design and analysis, covering thermal, mechanical, electrical, and reliability modeling. ## 1. Thermal Modeling Thermal management is the most critical aspect of chip packaging. ### 1.1 Steady-State Heat Conduction (Fourier's Law) The fundamental heat conduction equation: $$ \nabla \cdot (k \nabla T) + Q = 0 $$ **Variable definitions:** - $k$ — thermal conductivity (W/m·K) - $T$ — temperature (K) - $Q$ — volumetric heat generation (W/m³) - $\nabla$ — gradient operator ### 1.2 Transient Heat Conduction For time-dependent analysis: $$ \rho c_p \frac{\partial T}{\partial t} = k \nabla^2 T + Q $$ **Where:** - $\rho$ — density (kg/m³) - $c_p$ — specific heat capacity (J/kg·K) - $t$ — time (s) ### 1.3 Thermal Resistance Network Model For practical package design, thermal resistance is defined as: $$ R_{th} = \frac{\Delta T}{P} $$ **Total junction-to-ambient resistance:** $$ R_{ja} = R_{jc} + R_{cs} + R_{sa} $$ **Component breakdown:** - $R_{jc}$ — junction-to-case resistance (°C/W) - $R_{cs}$ — case-to-sink resistance (°C/W) - $R_{sa}$ — sink-to-ambient resistance (°C/W) ### 1.4 Multi-Layer Thermal Resistance For a single layer: $$ R_{layer} = \frac{t}{k \cdot A} $$ **For series layers:** $$ R_{total} = \sum_{i=1}^{n} R_i = \sum_{i=1}^{n} \frac{t_i}{k_i \cdot A_i} $$ **For parallel heat paths:** $$ \frac{1}{R_{total}} = \sum_{i=1}^{n} \frac{1}{R_i} $$ ### 1.5 Convective Heat Transfer At package surfaces: $$ q = h \cdot A \cdot (T_s - T_{\infty}) $$ **Where:** - $h$ — convective heat transfer coefficient (W/m²·K) - $A$ — surface area (m²) - $T_s$ — surface temperature (K) - $T_{\infty}$ — ambient temperature (K) ## 2. Thermo-Mechanical Stress Modeling CTE mismatch between materials creates thermal stress. ### 2.1 Typical CTE Values | Material | CTE (ppm/°C) | |----------|--------------| | Silicon | 2.6 | | Copper | 17 | | Organic Substrate | 14–17 | | Solder (SAC305) | 21 | | Underfill | 25–40 | ### 2.2 Thermal Strain from CTE Mismatch $$ \varepsilon_{thermal} = \Delta\alpha \cdot \Delta T $$ **Where:** - $\varepsilon_{thermal}$ — thermal strain (dimensionless) - $\Delta\alpha$ — CTE difference (ppm/°C) - $\Delta T$ — temperature change (°C) ### 2.3 Thermal Stress $$ \sigma = E \cdot \varepsilon = E \cdot \Delta\alpha \cdot \Delta T $$ **Where:** - $\sigma$ — stress (Pa or MPa) - $E$ — Young's modulus (Pa or GPa) ### 2.4 Warpage Modeling (Stoney's Equation) For thin film stress on substrate: $$ \sigma_f = \frac{E_s \cdot t_s^2}{6(1-\nu_s) \cdot t_f \cdot R} $$ **Variable definitions:** - $\sigma_f$ — film stress (Pa) - $E_s$ — substrate Young's modulus (Pa) - $t_s$ — substrate thickness (m) - $t_f$ — film thickness (m) - $\nu_s$ — substrate Poisson's ratio (dimensionless) - $R$ — radius of curvature (m) ### 2.5 Bi-Material Strip Curvature $$ \kappa = \frac{1}{R} = \frac{6(\alpha_1 - \alpha_2)(T - T_0)(1 + m)^2}{h \left[ 3(1+m)^2 + (1+mn)\left( m^2 + \frac{1}{mn} \right) \right]} $$ **Where:** - $m = \frac{t_1}{t_2}$ — thickness ratio - $n = \frac{E_1}{E_2}$ — modulus ratio - $h = t_1 + t_2$ — total thickness ### 2.6 Solder Joint Shear Strain Distance to neutral point (DNP) model: $$ \gamma = \frac{D_N \cdot \Delta\alpha \cdot \Delta T}{h} $$ **Where:** - $\gamma$ — shear strain (dimensionless) - $D_N$ — distance to neutral point (mm) - $h$ — solder bump/joint height (mm) ### 2.7 Coffin-Manson Fatigue Model Cycles to failure: $$ N_f = C \cdot (\Delta \gamma_p)^{-n} $$ **Where:** - $N_f$ — number of cycles to failure - $\Delta \gamma_p$ — plastic shear strain range - $C$ — fatigue ductility coefficient - $n$ — fatigue exponent (typically 1.9–2.5) ### 2.8 Engelmaier Model for Solder Fatigue $$ N_f = \frac{1}{2} \left( \frac{\Delta \gamma}{2 \varepsilon_f'} \right)^{1/c} $$ **Where:** $$ c = -0.442 - 6 \times 10^{-4} T_{SJ} + 1.74 \times 10^{-2} \ln(1 + f) $$ - $T_{SJ}$ — mean solder joint temperature (°C) - $f$ — cyclic frequency (cycles/day) - $\varepsilon_f'$ — fatigue ductility coefficient ## 3. Electrical Modeling ### 3.1 Transmission Line Theory For high-frequency interconnects, characteristic impedance: $$ Z_0 = \sqrt{\frac{L}{C}} = \sqrt{\frac{R + j\omega L}{G + j\omega C}} $$ **Where:** - $Z_0$ — characteristic impedance (Ω) - $L$ — inductance per unit length (H/m) - $C$ — capacitance per unit length (F/m) - $R$ — resistance per unit length (Ω/m) - $G$ — conductance per unit length (S/m) - $\omega$ — angular frequency (rad/s) ### 3.2 Microstrip Impedance Approximate formula: $$ Z_0 \approx \frac{87}{\sqrt{\varepsilon_r + 1.41}} \ln\left(\frac{5.98h}{0.8w + t}\right) $$ **Where:** - $\varepsilon_r$ — relative permittivity of dielectric - $h$ — dielectric thickness (mm) - $w$ — trace width (mm) - $t$ — trace thickness (mm) ### 3.3 Stripline Impedance $$ Z_0 \approx \frac{60}{\sqrt{\varepsilon_r}} \ln\left(\frac{4b}{\pi d}\right) $$ **Where:** - $b$ — distance between ground planes - $d$ — trace width ### 3.4 Propagation Delay $$ t_{pd} = l \sqrt{LC} = \frac{l \sqrt{\varepsilon_{eff}}}{c} $$ **Where:** - $t_{pd}$ — propagation delay (s) - $l$ — trace length (m) - $\varepsilon_{eff}$ — effective dielectric constant - $c$ — speed of light ($3 \times 10^8$ m/s) ### 3.5 Effective Dielectric Constant (Microstrip) $$ \varepsilon_{eff} = \frac{\varepsilon_r + 1}{2} + \frac{\varepsilon_r - 1}{2} \cdot \frac{1}{\sqrt{1 + 12h/w}} $$ ### 3.6 Skin Effect Resistance At high frequencies: $$ R_{AC} = R_{DC} \cdot \frac{t}{\delta} \quad \text{for } t > 2\delta $$ **Skin depth:** $$ \delta = \sqrt{\frac{2\rho}{\omega \mu}} = \sqrt{\frac{\rho}{\pi f \mu}} $$ **Where:** - $\delta$ — skin depth (m) - $\rho$ — resistivity (Ω·m) - $\mu$ — permeability (H/m) - $f$ — frequency (Hz) ### 3.7 Power Delivery Network (PDN) **Target impedance:** $$ Z_{target} = \frac{V_{DD} \cdot \text{ripple\%}}{I_{max} \cdot \text{transient\%}} $$ **Example calculation:** - $V_{DD} = 1.0$ V - Allowed ripple = 5% - $I_{max} = 10$ A - Transient = 50% $$ Z_{target} = \frac{1.0 \times 0.05}{10 \times 0.5} = 10 \text{ m}\Omega $$ ### 3.8 Decoupling Capacitor Resonance $$ f_{res} = \frac{1}{2\pi\sqrt{LC}} $$ **Impedance of capacitor with ESL and ESR:** $$ Z_{cap}(f) = ESR + j\left(2\pi f \cdot ESL - \frac{1}{2\pi f \cdot C}\right) $$ ### 3.9 Inductance of Bond Wire Approximate formula: $$ L \approx 0.2 l \left[ \ln\left(\frac{2l}{r}\right) - 0.75 \right] \text{ (nH)} $$ **Where:** - $l$ — wire length (mm) - $r$ — wire radius (mm) ### 3.10 Via Inductance $$ L_{via} \approx \frac{\mu_0 h}{2\pi} \left[ \ln\left(\frac{4h}{d}\right) + 1 \right] $$ **Where:** - $h$ — via height (m) - $d$ — via diameter (m) - $\mu_0 = 4\pi \times 10^{-7}$ H/m ## 4. Interconnect Density and Routing ### 4.1 Rent's Rule Empirical relationship between I/O and gates: $$ P = K \cdot G^p $$ **Where:** - $P$ — number of I/O pins - $G$ — number of gates (or logic blocks) - $K$ — Rent's coefficient (typically 3–6) - $p$ — Rent's exponent (typically 0.5–0.7) ### 4.2 Wire Length Estimation **Average wire length in 2D:** $$ \bar{L} = \alpha \sqrt{A} $$ **Where:** - $\bar{L}$ — average wire length - $A$ — chip area - $\alpha$ — constant (typically 0.5–1.0) ### 4.3 Donath's Model for Average Wire Length $$ \bar{L} = \frac{2}{3} \cdot \frac{p}{p-1} \cdot G^{(p-0.5)} \cdot d $$ **Where:** - $d$ — average gate pitch - $p$ — Rent's exponent ### 4.4 Number of Routing Layers $$ N_{layers} \approx \frac{L_{total} \cdot f_{utilization}}{A_{chip} / P_{track}} $$ **Where:** - $L_{total}$ — total wire length required - $f_{utilization}$ — routing utilization factor (typically 0.5–0.7) - $P_{track}$ — routing track pitch ### 4.5 I/O Pitch and Bandwidth **Maximum I/O count for area array:** $$ N_{IO} = \left(\frac{D}{P}\right)^2 $$ **Where:** - $D$ — die size (mm) - $P$ — bump pitch (mm) ## 5. Reliability Modeling ### 5.1 Arrhenius Equation (Temperature Acceleration) $$ AF = \exp\left[\frac{E_a}{k}\left(\frac{1}{T_{use}} - \frac{1}{T_{stress}}\right)\right] $$ **Where:** - $AF$ — acceleration factor - $E_a$ — activation energy (eV) - $k$ — Boltzmann constant ($8.617 \times 10^{-5}$ eV/K) - $T$ — absolute temperature (K) ### 5.2 Black's Equation (Electromigration) $$ MTTF = A \cdot j^{-n} \cdot \exp\left(\frac{E_a}{kT}\right) $$ **Where:** - $MTTF$ — mean time to failure (hours) - $j$ — current density (A/cm² or MA/cm²) - $n$ — current density exponent (typically 1–2) - $A$ — material constant - $E_a$ — activation energy (typically 0.7–0.9 eV for Al, 0.9–1.0 eV for Cu) ### 5.3 Maximum Allowed Current Density From Black's equation, for target lifetime: $$ j_{max} = \left(\frac{A \cdot \exp(E_a/kT)}{MTTF_{target}}\right)^{1/n} $$ ### 5.4 Weibull Distribution **Cumulative failure probability:** $$ F(t) = 1 - \exp\left[-\left(\frac{t}{\eta}\right)^\beta\right] $$ **Probability density function:** $$ f(t) = \frac{\beta}{\eta}\left(\frac{t}{\eta}\right)^{\beta-1} \exp\left[-\left(\frac{t}{\eta}\right)^\beta\right] $$ **Where:** - $F(t)$ — cumulative distribution function - $\eta$ — scale parameter (characteristic life at 63.2% failure) - $\beta$ — shape parameter (Weibull slope) - $\beta < 1$: infant mortality - $\beta = 1$: random failures (exponential) - $\beta > 1$: wear-out failures ### 5.5 MTTF from Weibull Parameters $$ MTTF = \eta \cdot \Gamma\left(1 + \frac{1}{\beta}\right) $$ **Where:** - $\Gamma$ — gamma function ### 5.6 Norris-Landzberg Acceleration Model For thermal cycling: $$ AF = \left(\frac{f_{use}}{f_{test}}\right)^{m_1} \left(\frac{\Delta T_{test}}{\Delta T_{use}}\right)^{m_2} \exp\left[\frac{E_a}{k}\left(\frac{1}{T_{max,use}} - \frac{1}{T_{max,test}}\right)\right] $$ **Where:** - $f$ — cycling frequency - $\Delta T$ — temperature range - $m_1, m_2$ — empirical exponents ### 5.7 JEDEC Moisture Sensitivity Level (MSL) **Moisture diffusion (Fick's law):** $$ \frac{\partial C}{\partial t} = D \nabla^2 C $$ **Diffusion coefficient temperature dependence:** $$ D = D_0 \exp\left(-\frac{E_a}{kT}\right) $$ ## 6. Advanced Packaging: 3D Integration ### 6.1 Thermal Modeling in 3D Stacks **3D heat equation:** $$ \rho c_p \frac{\partial T}{\partial t} = k_x\frac{\partial^2 T}{\partial x^2} + k_y\frac{\partial^2 T}{\partial y^2} + k_z\frac{\partial^2 T}{\partial z^2} + Q(x,y,z,t) $$ ### 6.2 Effective Vertical Thermal Conductivity with TSVs $$ k_{eff,z} = k_{Si}(1-\phi) + k_{Cu} \cdot \phi $$ **Where:** - $\phi$ — TSV area density (TSV area / total area) - $k_{Si} \approx 148$ W/m·K - $k_{Cu} \approx 400$ W/m·K ### 6.3 TSV Electrical Resistance $$ R_{TSV} = \frac{\rho \cdot L}{\pi r^2} $$ **Where:** - $\rho$ — resistivity of TSV fill material (Ω·m) - $L$ — TSV length (m) - $r$ — TSV radius (m) ### 6.4 TSV Capacitance (MOS Model) $$ C_{TSV} = \frac{2\pi\varepsilon_{ox} L}{\ln(r_{ox}/r_{TSV})} + C_{depletion} $$ **Where:** - $\varepsilon_{ox}$ — oxide permittivity - $r_{ox}$ — outer radius (TSV + oxide) - $r_{TSV}$ — TSV radius ### 6.5 TSV Inductance $$ L_{TSV} \approx \frac{\mu_0 L}{2\pi}\left[\ln\left(\frac{2L}{r}\right) - 1\right] $$ ### 6.6 Yield Modeling **Single die yield (Poisson model):** $$ Y = e^{-D \cdot A} $$ **Murphy's model:** $$ Y = \left(\frac{1 - e^{-D \cdot A}}{D \cdot A}\right)^2 $$ **Where:** - $D$ — defect density (defects/cm²) - $A$ — die area (cm²) ### 6.7 Chiplet vs. Monolithic Yield Comparison **Monolithic die:** $$ Y_{mono} = Y_0 \cdot e^{-D \cdot A} $$ **Chiplet approach (n identical chiplets):** $$ Y_{chiplet} = \left(Y_0 \cdot e^{-D \cdot A/n}\right)^n \cdot Y_{assembly} $$ **Chiplet advantage condition:** $$ \left(e^{-D \cdot A/n}\right)^n \cdot Y_{assembly} > e^{-D \cdot A} $$ ### 6.8 Known Good Die (KGD) Economics **Cost model:** $$ Cost_{chiplet} = n \cdot \frac{C_{wafer}}{N_{die} \cdot Y_{chiplet}} + C_{assembly} + C_{test} $$ ## 7. Optimization Framework ### 7.1 Multi-Objective Optimization Problem $$ \min_{\mathbf{x}} \left[ f_{thermal}(\mathbf{x}), f_{stress}(\mathbf{x}), f_{electrical}(\mathbf{x}), f_{cost}(\mathbf{x}) \right] $$ ### 7.2 Design Constraints **Thermal constraint:** $$ T_{junction}(\mathbf{x}) \leq T_{max} $$ **Mechanical constraint:** $$ \sigma_{max}(\mathbf{x}) \leq \sigma_{allowable} $$ **Electrical constraint:** $$ Z_{PDN}(f, \mathbf{x}) \leq Z_{target} \quad \forall f \in [f_{min}, f_{max}] $$ **Geometric constraints:** $$ \begin{aligned} P_{bump} &\geq P_{min} \\ N_{layers} &\leq N_{max} \\ t_{package} &\leq t_{max} \end{aligned} $$ ### 7.3 Lagrangian Formulation $$ \mathcal{L}(\mathbf{x}, \boldsymbol{\lambda}) = \sum_{i} w_i f_i(\mathbf{x}) + \sum_{j} \lambda_j g_j(\mathbf{x}) $$ **Where:** - $w_i$ — weight for objective $i$ - $\lambda_j$ — Lagrange multiplier for constraint $j$ - $g_j(\mathbf{x}) \leq 0$ — inequality constraints ### 7.4 Pareto Optimality A solution $\mathbf{x}^*$ is Pareto optimal if there exists no $\mathbf{x}$ such that: $$ f_i(\mathbf{x}) \leq f_i(\mathbf{x}^*) \quad \forall i $$ and $$ f_j(\mathbf{x}) < f_j(\mathbf{x}^*) \quad \text{for at least one } j $$ ## 8. Summary Tables ### 8.1 Key Equations by Domain | Domain | Key Equation | Primary Variables | |--------|--------------|-------------------| | Thermal | $R_{th} = \Delta T / P$ | $k$, $T$, $R_{th}$ | | Mechanical | $\sigma = E \cdot \Delta\alpha \cdot \Delta T$ | $\sigma$, $\varepsilon$, CTE | | Electrical | $Z_0 = \sqrt{L/C}$ | $Z_0$, $L$, $C$, $R$ | | Reliability | $MTTF = A \cdot j^{-n} \cdot e^{E_a/kT}$ | $j$, MTTF, $N_f$ | | Yield | $Y = e^{-D \cdot A}$ | $D$, $A$, yield | ### 8.2 Typical Material Properties | Property | Silicon | Copper | FR-4 | SAC305 | |----------|---------|--------|------|--------| | $k$ (W/m·K) | 148 | 400 | 0.3 | 58 | | CTE (ppm/°C) | 2.6 | 17 | 14–17 | 21 | | $E$ (GPa) | 130 | 120 | 22 | 45 | | $\rho$ (μΩ·cm) | — | 1.7 | — | 11 | ### 8.3 Design Rules of Thumb | Parameter | Typical Range | |-----------|---------------| | Junction-to-ambient $R_{th}$ | 20–50 °C/W | | Solder joint height | 50–100 μm | | Bump pitch (advanced) | 40–150 μm | | TSV diameter | 5–50 μm | | PDN target impedance | 1–10 mΩ | | Skin depth (Cu @ 1 GHz) | ~2 μm | ## Mathematical Notation Reference | Symbol | Description | Units | |--------|-------------|-------| | $T$ | Temperature | K or °C | | $k$ | Thermal conductivity | W/m·K | | $\alpha$ | Coefficient of thermal expansion | ppm/°C | | $\sigma$ | Stress | Pa, MPa | | $\varepsilon$ | Strain | dimensionless | | $E$ | Young's modulus | Pa, GPa | | $\nu$ | Poisson's ratio | dimensionless | | $Z_0$ | Characteristic impedance | Ω | | $L$ | Inductance | H | | $C$ | Capacitance | F | | $R$ | Resistance | Ω | | $j$ | Current density | A/cm² | | $\rho$ | Resistivity | Ω·m | | $D$ | Defect density | defects/cm² |
# Chip Packaging ## Mathematical Modeling Mathematical frameworks used in chip packaging design and analysis, covering thermal, mechanical, electrical, and reliability modeling. ## 1. Thermal Modeling Thermal management is the most critical aspect of chip packaging. ### 1.1 Steady-State Heat Conduction (Fourier's Law) The fundamental heat conduction equation: $$ \nabla \cdot (k \nabla T) + Q = 0 $$ **Variable definitions:** - $k$ — thermal conductivity (W/m·K) - $T$ — temperature (K) - $Q$ — volumetric heat generation (W/m³) - $\nabla$ — gradient operator ### 1.2 Transient Heat Conduction For time-dependent analysis: $$ \rho c_p \frac{\partial T}{\partial t} = k \nabla^2 T + Q $$ **Where:** - $\rho$ — density (kg/m³) - $c_p$ — specific heat capacity (J/kg·K) - $t$ — time (s) ### 1.3 Thermal Resistance Network Model For practical package design, thermal resistance is defined as: $$ R_{th} = \frac{\Delta T}{P} $$ **Total junction-to-ambient resistance:** $$ R_{ja} = R_{jc} + R_{cs} + R_{sa} $$ **Component breakdown:** - $R_{jc}$ — junction-to-case resistance (°C/W) - $R_{cs}$ — case-to-sink resistance (°C/W) - $R_{sa}$ — sink-to-ambient resistance (°C/W) ### 1.4 Multi-Layer Thermal Resistance For a single layer: $$ R_{layer} = \frac{t}{k \cdot A} $$ **For series layers:** $$ R_{total} = \sum_{i=1}^{n} R_i = \sum_{i=1}^{n} \frac{t_i}{k_i \cdot A_i} $$ **For parallel heat paths:** $$ \frac{1}{R_{total}} = \sum_{i=1}^{n} \frac{1}{R_i} $$ ### 1.5 Convective Heat Transfer At package surfaces: $$ q = h \cdot A \cdot (T_s - T_{\infty}) $$ **Where:** - $h$ — convective heat transfer coefficient (W/m²·K) - $A$ — surface area (m²) - $T_s$ — surface temperature (K) - $T_{\infty}$ — ambient temperature (K) ## 2. Thermo-Mechanical Stress Modeling CTE mismatch between materials creates thermal stress. ### 2.1 Typical CTE Values | Material | CTE (ppm/°C) | |----------|--------------| | Silicon | 2.6 | | Copper | 17 | | Organic Substrate | 14–17 | | Solder (SAC305) | 21 | | Underfill | 25–40 | ### 2.2 Thermal Strain from CTE Mismatch $$ \varepsilon_{thermal} = \Delta\alpha \cdot \Delta T $$ **Where:** - $\varepsilon_{thermal}$ — thermal strain (dimensionless) - $\Delta\alpha$ — CTE difference (ppm/°C) - $\Delta T$ — temperature change (°C) ### 2.3 Thermal Stress $$ \sigma = E \cdot \varepsilon = E \cdot \Delta\alpha \cdot \Delta T $$ **Where:** - $\sigma$ — stress (Pa or MPa) - $E$ — Young's modulus (Pa or GPa) ### 2.4 Warpage Modeling (Stoney's Equation) For thin film stress on substrate: $$ \sigma_f = \frac{E_s \cdot t_s^2}{6(1-\nu_s) \cdot t_f \cdot R} $$ **Variable definitions:** - $\sigma_f$ — film stress (Pa) - $E_s$ — substrate Young's modulus (Pa) - $t_s$ — substrate thickness (m) - $t_f$ — film thickness (m) - $\nu_s$ — substrate Poisson's ratio (dimensionless) - $R$ — radius of curvature (m) ### 2.5 Bi-Material Strip Curvature $$ \kappa = \frac{1}{R} = \frac{6(\alpha_1 - \alpha_2)(T - T_0)(1 + m)^2}{h \left[ 3(1+m)^2 + (1+mn)\left( m^2 + \frac{1}{mn} \right) \right]} $$ **Where:** - $m = \frac{t_1}{t_2}$ — thickness ratio - $n = \frac{E_1}{E_2}$ — modulus ratio - $h = t_1 + t_2$ — total thickness ### 2.6 Solder Joint Shear Strain Distance to neutral point (DNP) model: $$ \gamma = \frac{D_N \cdot \Delta\alpha \cdot \Delta T}{h} $$ **Where:** - $\gamma$ — shear strain (dimensionless) - $D_N$ — distance to neutral point (mm) - $h$ — solder bump/joint height (mm) ### 2.7 Coffin-Manson Fatigue Model Cycles to failure: $$ N_f = C \cdot (\Delta \gamma_p)^{-n} $$ **Where:** - $N_f$ — number of cycles to failure - $\Delta \gamma_p$ — plastic shear strain range - $C$ — fatigue ductility coefficient - $n$ — fatigue exponent (typically 1.9–2.5) ### 2.8 Engelmaier Model for Solder Fatigue $$ N_f = \frac{1}{2} \left( \frac{\Delta \gamma}{2 \varepsilon_f'} \right)^{1/c} $$ **Where:** $$ c = -0.442 - 6 \times 10^{-4} T_{SJ} + 1.74 \times 10^{-2} \ln(1 + f) $$ - $T_{SJ}$ — mean solder joint temperature (°C) - $f$ — cyclic frequency (cycles/day) - $\varepsilon_f'$ — fatigue ductility coefficient ## 3. Electrical Modeling ### 3.1 Transmission Line Theory For high-frequency interconnects, characteristic impedance: $$ Z_0 = \sqrt{\frac{L}{C}} = \sqrt{\frac{R + j\omega L}{G + j\omega C}} $$ **Where:** - $Z_0$ — characteristic impedance (Ω) - $L$ — inductance per unit length (H/m) - $C$ — capacitance per unit length (F/m) - $R$ — resistance per unit length (Ω/m) - $G$ — conductance per unit length (S/m) - $\omega$ — angular frequency (rad/s) ### 3.2 Microstrip Impedance Approximate formula: $$ Z_0 \approx \frac{87}{\sqrt{\varepsilon_r + 1.41}} \ln\left(\frac{5.98h}{0.8w + t}\right) $$ **Where:** - $\varepsilon_r$ — relative permittivity of dielectric - $h$ — dielectric thickness (mm) - $w$ — trace width (mm) - $t$ — trace thickness (mm) ### 3.3 Stripline Impedance $$ Z_0 \approx \frac{60}{\sqrt{\varepsilon_r}} \ln\left(\frac{4b}{\pi d}\right) $$ **Where:** - $b$ — distance between ground planes - $d$ — trace width ### 3.4 Propagation Delay $$ t_{pd} = l \sqrt{LC} = \frac{l \sqrt{\varepsilon_{eff}}}{c} $$ **Where:** - $t_{pd}$ — propagation delay (s) - $l$ — trace length (m) - $\varepsilon_{eff}$ — effective dielectric constant - $c$ — speed of light ($3 \times 10^8$ m/s) ### 3.5 Effective Dielectric Constant (Microstrip) $$ \varepsilon_{eff} = \frac{\varepsilon_r + 1}{2} + \frac{\varepsilon_r - 1}{2} \cdot \frac{1}{\sqrt{1 + 12h/w}} $$ ### 3.6 Skin Effect Resistance At high frequencies: $$ R_{AC} = R_{DC} \cdot \frac{t}{\delta} \quad \text{for } t > 2\delta $$ **Skin depth:** $$ \delta = \sqrt{\frac{2\rho}{\omega \mu}} = \sqrt{\frac{\rho}{\pi f \mu}} $$ **Where:** - $\delta$ — skin depth (m) - $\rho$ — resistivity (Ω·m) - $\mu$ — permeability (H/m) - $f$ — frequency (Hz) ### 3.7 Power Delivery Network (PDN) **Target impedance:** $$ Z_{target} = \frac{V_{DD} \cdot \text{ripple\%}}{I_{max} \cdot \text{transient\%}} $$ **Example calculation:** - $V_{DD} = 1.0$ V - Allowed ripple = 5% - $I_{max} = 10$ A - Transient = 50% $$ Z_{target} = \frac{1.0 \times 0.05}{10 \times 0.5} = 10 \text{ m}\Omega $$ ### 3.8 Decoupling Capacitor Resonance $$ f_{res} = \frac{1}{2\pi\sqrt{LC}} $$ **Impedance of capacitor with ESL and ESR:** $$ Z_{cap}(f) = ESR + j\left(2\pi f \cdot ESL - \frac{1}{2\pi f \cdot C}\right) $$ ### 3.9 Inductance of Bond Wire Approximate formula: $$ L \approx 0.2 l \left[ \ln\left(\frac{2l}{r}\right) - 0.75 \right] \text{ (nH)} $$ **Where:** - $l$ — wire length (mm) - $r$ — wire radius (mm) ### 3.10 Via Inductance $$ L_{via} \approx \frac{\mu_0 h}{2\pi} \left[ \ln\left(\frac{4h}{d}\right) + 1 \right] $$ **Where:** - $h$ — via height (m) - $d$ — via diameter (m) - $\mu_0 = 4\pi \times 10^{-7}$ H/m ## 4. Interconnect Density and Routing ### 4.1 Rent's Rule Empirical relationship between I/O and gates: $$ P = K \cdot G^p $$ **Where:** - $P$ — number of I/O pins - $G$ — number of gates (or logic blocks) - $K$ — Rent's coefficient (typically 3–6) - $p$ — Rent's exponent (typically 0.5–0.7) ### 4.2 Wire Length Estimation **Average wire length in 2D:** $$ \bar{L} = \alpha \sqrt{A} $$ **Where:** - $\bar{L}$ — average wire length - $A$ — chip area - $\alpha$ — constant (typically 0.5–1.0) ### 4.3 Donath's Model for Average Wire Length $$ \bar{L} = \frac{2}{3} \cdot \frac{p}{p-1} \cdot G^{(p-0.5)} \cdot d $$ **Where:** - $d$ — average gate pitch - $p$ — Rent's exponent ### 4.4 Number of Routing Layers $$ N_{layers} \approx \frac{L_{total} \cdot f_{utilization}}{A_{chip} / P_{track}} $$ **Where:** - $L_{total}$ — total wire length required - $f_{utilization}$ — routing utilization factor (typically 0.5–0.7) - $P_{track}$ — routing track pitch ### 4.5 I/O Pitch and Bandwidth **Maximum I/O count for area array:** $$ N_{IO} = \left(\frac{D}{P}\right)^2 $$ **Where:** - $D$ — die size (mm) - $P$ — bump pitch (mm) ## 5. Reliability Modeling ### 5.1 Arrhenius Equation (Temperature Acceleration) $$ AF = \exp\left[\frac{E_a}{k}\left(\frac{1}{T_{use}} - \frac{1}{T_{stress}}\right)\right] $$ **Where:** - $AF$ — acceleration factor - $E_a$ — activation energy (eV) - $k$ — Boltzmann constant ($8.617 \times 10^{-5}$ eV/K) - $T$ — absolute temperature (K) ### 5.2 Black's Equation (Electromigration) $$ MTTF = A \cdot j^{-n} \cdot \exp\left(\frac{E_a}{kT}\right) $$ **Where:** - $MTTF$ — mean time to failure (hours) - $j$ — current density (A/cm² or MA/cm²) - $n$ — current density exponent (typically 1–2) - $A$ — material constant - $E_a$ — activation energy (typically 0.7–0.9 eV for Al, 0.9–1.0 eV for Cu) ### 5.3 Maximum Allowed Current Density From Black's equation, for target lifetime: $$ j_{max} = \left(\frac{A \cdot \exp(E_a/kT)}{MTTF_{target}}\right)^{1/n} $$ ### 5.4 Weibull Distribution **Cumulative failure probability:** $$ F(t) = 1 - \exp\left[-\left(\frac{t}{\eta}\right)^\beta\right] $$ **Probability density function:** $$ f(t) = \frac{\beta}{\eta}\left(\frac{t}{\eta}\right)^{\beta-1} \exp\left[-\left(\frac{t}{\eta}\right)^\beta\right] $$ **Where:** - $F(t)$ — cumulative distribution function - $\eta$ — scale parameter (characteristic life at 63.2% failure) - $\beta$ — shape parameter (Weibull slope) - $\beta < 1$: infant mortality - $\beta = 1$: random failures (exponential) - $\beta > 1$: wear-out failures ### 5.5 MTTF from Weibull Parameters $$ MTTF = \eta \cdot \Gamma\left(1 + \frac{1}{\beta}\right) $$ **Where:** - $\Gamma$ — gamma function ### 5.6 Norris-Landzberg Acceleration Model For thermal cycling: $$ AF = \left(\frac{f_{use}}{f_{test}}\right)^{m_1} \left(\frac{\Delta T_{test}}{\Delta T_{use}}\right)^{m_2} \exp\left[\frac{E_a}{k}\left(\frac{1}{T_{max,use}} - \frac{1}{T_{max,test}}\right)\right] $$ **Where:** - $f$ — cycling frequency - $\Delta T$ — temperature range - $m_1, m_2$ — empirical exponents ### 5.7 JEDEC Moisture Sensitivity Level (MSL) **Moisture diffusion (Fick's law):** $$ \frac{\partial C}{\partial t} = D \nabla^2 C $$ **Diffusion coefficient temperature dependence:** $$ D = D_0 \exp\left(-\frac{E_a}{kT}\right) $$ ## 6. Advanced Packaging: 3D Integration ### 6.1 Thermal Modeling in 3D Stacks **3D heat equation:** $$ \rho c_p \frac{\partial T}{\partial t} = k_x\frac{\partial^2 T}{\partial x^2} + k_y\frac{\partial^2 T}{\partial y^2} + k_z\frac{\partial^2 T}{\partial z^2} + Q(x,y,z,t) $$ ### 6.2 Effective Vertical Thermal Conductivity with TSVs $$ k_{eff,z} = k_{Si}(1-\phi) + k_{Cu} \cdot \phi $$ **Where:** - $\phi$ — TSV area density (TSV area / total area) - $k_{Si} \approx 148$ W/m·K - $k_{Cu} \approx 400$ W/m·K ### 6.3 TSV Electrical Resistance $$ R_{TSV} = \frac{\rho \cdot L}{\pi r^2} $$ **Where:** - $\rho$ — resistivity of TSV fill material (Ω·m) - $L$ — TSV length (m) - $r$ — TSV radius (m) ### 6.4 TSV Capacitance (MOS Model) $$ C_{TSV} = \frac{2\pi\varepsilon_{ox} L}{\ln(r_{ox}/r_{TSV})} + C_{depletion} $$ **Where:** - $\varepsilon_{ox}$ — oxide permittivity - $r_{ox}$ — outer radius (TSV + oxide) - $r_{TSV}$ — TSV radius ### 6.5 TSV Inductance $$ L_{TSV} \approx \frac{\mu_0 L}{2\pi}\left[\ln\left(\frac{2L}{r}\right) - 1\right] $$ ### 6.6 Yield Modeling **Single die yield (Poisson model):** $$ Y = e^{-D \cdot A} $$ **Murphy's model:** $$ Y = \left(\frac{1 - e^{-D \cdot A}}{D \cdot A}\right)^2 $$ **Where:** - $D$ — defect density (defects/cm²) - $A$ — die area (cm²) ### 6.7 Chiplet vs. Monolithic Yield Comparison **Monolithic die:** $$ Y_{mono} = Y_0 \cdot e^{-D \cdot A} $$ **Chiplet approach (n identical chiplets):** $$ Y_{chiplet} = \left(Y_0 \cdot e^{-D \cdot A/n}\right)^n \cdot Y_{assembly} $$ **Chiplet advantage condition:** $$ \left(e^{-D \cdot A/n}\right)^n \cdot Y_{assembly} > e^{-D \cdot A} $$ ### 6.8 Known Good Die (KGD) Economics **Cost model:** $$ Cost_{chiplet} = n \cdot \frac{C_{wafer}}{N_{die} \cdot Y_{chiplet}} + C_{assembly} + C_{test} $$ ## 7. Optimization Framework ### 7.1 Multi-Objective Optimization Problem $$ \min_{\mathbf{x}} \left[ f_{thermal}(\mathbf{x}), f_{stress}(\mathbf{x}), f_{electrical}(\mathbf{x}), f_{cost}(\mathbf{x}) \right] $$ ### 7.2 Design Constraints **Thermal constraint:** $$ T_{junction}(\mathbf{x}) \leq T_{max} $$ **Mechanical constraint:** $$ \sigma_{max}(\mathbf{x}) \leq \sigma_{allowable} $$ **Electrical constraint:** $$ Z_{PDN}(f, \mathbf{x}) \leq Z_{target} \quad \forall f \in [f_{min}, f_{max}] $$ **Geometric constraints:** $$ \begin{aligned} P_{bump} &\geq P_{min} \\ N_{layers} &\leq N_{max} \\ t_{package} &\leq t_{max} \end{aligned} $$ ### 7.3 Lagrangian Formulation $$ \mathcal{L}(\mathbf{x}, \boldsymbol{\lambda}) = \sum_{i} w_i f_i(\mathbf{x}) + \sum_{j} \lambda_j g_j(\mathbf{x}) $$ **Where:** - $w_i$ — weight for objective $i$ - $\lambda_j$ — Lagrange multiplier for constraint $j$ - $g_j(\mathbf{x}) \leq 0$ — inequality constraints ### 7.4 Pareto Optimality A solution $\mathbf{x}^*$ is Pareto optimal if there exists no $\mathbf{x}$ such that: $$ f_i(\mathbf{x}) \leq f_i(\mathbf{x}^*) \quad \forall i $$ and $$ f_j(\mathbf{x}) < f_j(\mathbf{x}^*) \quad \text{for at least one } j $$ ## 8. Summary Tables ### 8.1 Key Equations by Domain | Domain | Key Equation | Primary Variables | |--------|--------------|-------------------| | Thermal | $R_{th} = \Delta T / P$ | $k$, $T$, $R_{th}$ | | Mechanical | $\sigma = E \cdot \Delta\alpha \cdot \Delta T$ | $\sigma$, $\varepsilon$, CTE | | Electrical | $Z_0 = \sqrt{L/C}$ | $Z_0$, $L$, $C$, $R$ | | Reliability | $MTTF = A \cdot j^{-n} \cdot e^{E_a/kT}$ | $j$, MTTF, $N_f$ | | Yield | $Y = e^{-D \cdot A}$ | $D$, $A$, yield | ### 8.2 Typical Material Properties | Property | Silicon | Copper | FR-4 | SAC305 | |----------|---------|--------|------|--------| | $k$ (W/m·K) | 148 | 400 | 0.3 | 58 | | CTE (ppm/°C) | 2.6 | 17 | 14–17 | 21 | | $E$ (GPa) | 130 | 120 | 22 | 45 | | $\rho$ (μΩ·cm) | — | 1.7 | — | 11 | ### 8.3 Design Rules of Thumb | Parameter | Typical Range | |-----------|---------------| | Junction-to-ambient $R_{th}$ | 20–50 °C/W | | Solder joint height | 50–100 μm | | Bump pitch (advanced) | 40–150 μm | | TSV diameter | 5–50 μm | | PDN target impedance | 1–10 mΩ | | Skin depth (Cu @ 1 GHz) | ~2 μm | ## Mathematical Notation Reference | Symbol | Description | Units | |--------|-------------|-------| | $T$ | Temperature | K or °C | | $k$ | Thermal conductivity | W/m·K | | $\alpha$ | Coefficient of thermal expansion | ppm/°C | | $\sigma$ | Stress | Pa, MPa | | $\varepsilon$ | Strain | dimensionless | | $E$ | Young's modulus | Pa, GPa | | $\nu$ | Poisson's ratio | dimensionless | | $Z_0$ | Characteristic impedance | Ω | | $L$ | Inductance | H | | $C$ | Capacitance | F | | $R$ | Resistance | Ω | | $j$ | Current density | A/cm² | | $\rho$ | Resistivity | Ω·m | | $D$ | Defect density | defects/cm² |
Package size near die size.
Simulate chip and package together.
Build systems from multiple smaller dies.
Combining multiple chiplets.
Commercial exchange of chiplet designs.
Chiplets are small functional dies integrated in advanced packages.
Small modular die designed to be integrated with others.
US legislation providing funding to boost domestic semiconductor manufacturing.
Pattern using phase only without chrome.
Split crystal along natural planes.
Find defect clusters on wafer.
Cluster analysis groups adjacent failing die identifying localized defect sources.
Thermal expansion matching.
Interdigitated pattern for leakage testing.
Total uncertainty from all sources.
Compare dimensions to standard.
Packaging for automated placement.
# Semiconductor Material Mathematical Modeling **Materials Covered:** Germanium (Ge), Silicon (Si), Gallium Arsenide (GaAs), Silicon Carbide (SiC) ## 1. Material Properties Overview | Property | Si | Ge | GaAs | 4H-SiC | |:---------|:--:|:--:|:----:|:------:| | **Bandgap (eV)** | 1.12 (indirect) | 0.66 (indirect) | 1.42 (direct) | 3.26 (indirect) | | **Lattice constant (Å)** | 5.431 | 5.658 | 5.653 | a=3.07, c=10.05 | | **Electron mobility (cm²/V·s)** | 1400 | 3900 | 8500 | 1000 | | **Hole mobility (cm²/V·s)** | 450 | 1900 | 400 | 120 | | **Thermal conductivity (W/cm\cdotK)** | 1.5 | 0.6 | 0.5 | 4.9 | | **Melting point (°C)** | 1414 | 937 | 1238 | 2730 (sublimes) | | **Intrinsic carrier conc. (cm⁻³)** | $1.5 \times 10^{10}$ | $2.4 \times 10^{13}$ | $1.8 \times 10^{6}$ | $\sim 10^{-9}$ | ### Key Characteristics - **Silicon (Si)** - Most widely used semiconductor - Excellent native oxide ($\text{SiO}_2$) - Mature processing technology - Diamond cubic crystal structure - **Germanium (Ge)** - Higher carrier mobility than Si - Unstable native oxide (water-soluble) - Lower thermal budget (lower melting point) - Used for high-speed devices - **Gallium Arsenide (GaAs)** - Direct bandgap → optoelectronics - Highest electron mobility - No stable native oxide - III-V compound semiconductor - **Silicon Carbide (SiC)** - Wide bandgap → high-power applications - Excellent thermal conductivity - High breakdown field - Multiple polytypes (3C, 4H, 6H) ## 2. Crystal Growth ### 2.1 Czochralski (CZ) Method — Si, Ge, GaAs #### Heat Transfer in Melt The temperature distribution in the melt is governed by the convection-diffusion equation: $$ \rho c_p \frac{\partial T}{\partial t} + \rho c_p (\mathbf{v} \cdot \nabla)T = \nabla \cdot (k \nabla T) $$ **Where:** - $\rho$ — density (kg/m³) - $c_p$ — specific heat capacity (J/kg·K) - $T$ — temperature (K) - $\mathbf{v}$ — velocity field (m/s) - $k$ — thermal conductivity (W/m·K) #### Melt Convection Navier-Stokes equation with Boussinesq approximation for buoyancy: $$ \rho \left( \frac{\partial \mathbf{v}}{\partial t} + (\mathbf{v} \cdot \nabla)\mathbf{v} \right) = -\nabla p + \mu \nabla^2 \mathbf{v} + \rho \mathbf{g} \beta (T - T_m) $$ **Where:** - $p$ — pressure (Pa) - $\mu$ — dynamic viscosity (Pa·s) - $\mathbf{g}$ — gravitational acceleration (m/s²) - $\beta$ — thermal expansion coefficient (K⁻¹) - $T_m$ — melting temperature (K) #### Stefan Condition at Crystal-Melt Interface The interface position is determined by the heat balance: $$ k_s \left( \frac{\partial T}{\partial n} \right)_s - k_l \left( \frac{\partial T}{\partial n} \right)_l = \rho_s L v_n $$ **Where:** - $k_s$, $k_l$ — thermal conductivity of solid and liquid - $L$ — latent heat of fusion (J/kg) - $v_n$ — interface velocity normal to surface (m/s) - $\rho_s$ — solid density (kg/m³) #### Dopant Segregation — Burton-Prim-Slichter (BPS) Model The effective segregation coefficient accounts for boundary layer effects: $$ k_{\text{eff}} = \frac{k_0}{k_0 + (1-k_0)\exp\left( -\frac{v_g \delta}{D} \right)} $$ **Where:** - $k_0$ — equilibrium segregation coefficient (dimensionless) - $v_g$ — crystal growth rate (m/s) - $\delta$ — boundary layer thickness (m) - $D$ — diffusion coefficient in melt (m²/s) **Limiting cases:** - Slow growth ($v_g \delta / D \ll 1$): $k_{\text{eff}} \rightarrow k_0$ - Fast growth ($v_g \delta / D \gg 1$): $k_{\text{eff}} \rightarrow 1$ ### 2.2 Physical Vapor Transport (PVT) — SiC SiC sublimes rather than melts. Growth occurs via vapor species transport. #### Sublimation Species $$ \text{SiC}_{(s)} \rightleftharpoons \text{Si}_{(g)} + \text{C}_{(s)} $$ $$ 2\text{SiC}_{(s)} \rightleftharpoons \text{Si}_2\text{C}_{(g)} + \text{C}_{(s)} $$ $$ \text{SiC}_{(s)} + \text{Si}_{(g)} \rightleftharpoons \text{SiC}_2{}_{(g)} $$ #### Mass Transport Equation $$ \frac{\partial C_i}{\partial t} + \nabla \cdot (C_i \mathbf{v}) = \nabla \cdot (D_i \nabla C_i) + R_i $$ **Where:** - $C_i$ — concentration of species $i$ (mol/m³) - $D_i$ — diffusion coefficient of species $i$ (m²/s) - $R_i$ — reaction rate for species $i$ (mol/m³·s) #### Supersaturation at Growth Interface $$ \sigma = \frac{P_{\text{source}} - P_{\text{eq}}(T_{\text{seed}})}{P_{\text{eq}}(T_{\text{seed}})} $$ **Growth rate approximation:** $$ G \propto \frac{\sigma \cdot D}{L} $$ **Where:** - $L$ — source-to-seed distance (m) - $P_{\text{eq}}$ — equilibrium vapor pressure at seed temperature ## 3. Epitaxial Growth ### 3.1 Chemical Vapor Deposition (CVD) — Si, SiC #### Grove Model for Growth Rate $$ R = \frac{k_s C_g}{1 + \dfrac{k_s}{h_g}} $$ **Where:** - $R$ — growth rate (m/s) - $k_s$ — surface reaction rate constant (m/s) - $C_g$ — gas-phase reactant concentration (mol/m³) - $h_g$ — gas-phase mass transfer coefficient (m/s) #### Temperature Dependence (Arrhenius) $$ k_s = k_0 \exp\left(-\frac{E_a}{kT}\right) $$ **Where:** - $k_0$ — pre-exponential factor (m/s) - $E_a$ — activation energy (eV or J) - $k$ — Boltzmann constant ($8.617 \times 10^{-5}$ eV/K) - $T$ — temperature (K) #### Two Limiting Regimes | Regime | Condition | Growth Rate | Temperature Dependence | |:-------|:----------|:------------|:-----------------------| | **Reaction-limited** | $k_s \ll h_g$ | $R \approx k_s C_g$ | Strong (exponential) | | **Mass-transport-limited** | $k_s \gg h_g$ | $R \approx h_g C_g$ | Weak ($\sim T^{1/2}$) | #### Boundary Layer Thickness $$ \delta \approx \sqrt{\frac{\mu L}{\rho v}} = \sqrt{\frac{\nu L}{v}} $$ **Where:** - $\nu$ — kinematic viscosity (m²/s) - $L$ — characteristic length (m) - $v$ — gas flow velocity (m/s) **Mass transfer coefficient:** $$ h_g \approx \frac{D}{\delta} $$ ### 3.2 Molecular Beam Epitaxy (MBE) — GaAs, Ge #### Knudsen Cell Flux (Effusion) $$ J = \frac{P \cdot A_e \cdot \cos\theta}{\sqrt{2\pi m k T}} \cdot \frac{1}{\pi r^2} $$ **Where:** - $J$ — flux at substrate (atoms/cm²·s) - $P$ — vapor pressure in cell (Pa) - $A_e$ — effusion orifice area (m²) - $m$ — atomic mass (kg) - $r$ — source-to-substrate distance (m) - $\theta$ — angle from normal #### Growth Rate $$ R = \frac{J_{\text{Ga}}}{n_0} $$ **Where:** - $J_{\text{Ga}}$ — Ga flux at substrate (atoms/cm²·s) - $n_0$ — surface atomic density ($\sim 6.3 \times 10^{14}$ cm⁻² for GaAs (100)) #### Surface Diffusion **Diffusion coefficient:** $$ D_s = D_0 \exp\left(-\frac{E_d}{kT}\right) $$ **Mean diffusion length:** $$ \lambda = \sqrt{D_s \tau} $$ **Where:** - $E_d$ — diffusion activation energy (eV) - $\tau$ — residence time before desorption (s) ### 3.3 Heteroepitaxy — Critical Thickness For lattice-mismatched systems (e.g., Ge on Si with 4.2% mismatch): #### Matthews-Blakeslee Model $$ h_c = \frac{b}{2\pi f} \cdot \frac{1-\nu/4}{1+\nu} \cdot \ln\left(\frac{h_c}{b}\right) $$ **Where:** - $h_c$ — critical thickness for dislocation formation (m) - $b$ — Burgers vector magnitude (m) - $f$ — lattice mismatch: $f = \dfrac{a_{\text{layer}} - a_{\text{sub}}}{a_{\text{sub}}}$ - $\nu$ — Poisson's ratio (dimensionless) **Strain energy density:** $$ E_{\text{strain}} = \frac{E}{1-\nu} \cdot f^2 \cdot h $$ **Where:** - $E$ — Young's modulus (Pa) - $h$ — layer thickness (m) ## 4. Thermal Oxidation ### 4.1 Deal-Grove Model — Si The oxide thickness $x_{\text{ox}}$ as a function of time $t$: $$ x_{\text{ox}}^2 + A \cdot x_{\text{ox}} = B(t + \tau) $$ **Where:** - $A$, $B$ — rate constants (material and condition dependent) - $\tau$ — time correction for initial oxide: $\tau = \dfrac{x_i^2 + A \cdot x_i}{B}$ #### Parabolic Rate Constant $$ B = \frac{2 D_{\text{ox}} C^*}{N_1} $$ **Where:** - $D_{\text{ox}}$ — oxidant diffusivity in $\text{SiO}_2$ (m²/s) - $C^*$ — equilibrium oxidant concentration in oxide (mol/m³) - $N_1$ — number of oxidant molecules per unit volume of oxide #### Linear Rate Constant $$ \frac{B}{A} = \frac{k_s C^*}{N_1} $$ **Where:** - $k_s$ — surface reaction rate constant (m/s) #### Limiting Cases | Regime | Condition | Oxide Thickness | Rate Limiting Step | |:-------|:----------|:----------------|:-------------------| | **Linear** | $x_{\text{ox}} \ll A$ | $x_{\text{ox}} \approx \dfrac{B}{A} t$ | Surface reaction | | **Parabolic** | $x_{\text{ox}} \gg A$ | $x_{\text{ox}} \approx \sqrt{Bt}$ | Diffusion through oxide | #### Wet vs. Dry Oxidation | Parameter | Dry O₂ | Wet H₂O | |:----------|:-------|:--------| | $B$ (1000°C) | 0.0117 µm²/hr | 0.287 µm²/hr | | $B/A$ (1000°C) | 0.027 µm/hr | 0.96 µm/hr | | Oxide quality | Higher | Lower | | Growth rate | Slower (~10×) | Faster | ### 4.2 SiC Oxidation **Reaction:** $$ \text{SiC} + \frac{3}{2}\text{O}_2 \rightarrow \text{SiO}_2 + \text{CO} $$ **Key differences from Si:** - Oxidation rate is 10-100× slower than Si at the same temperature - Carbon removal adds complexity (CO must diffuse out) - Interface trap density ($D_{it}$) is a major challenge - Modified Deal-Grove models required: $$ x_{\text{ox}}^2 + A \cdot x_{\text{ox}} = B(t + \tau) + C \cdot t $$ The additional linear term $C \cdot t$ accounts for carbon-related interface reactions. ## 5. Diffusion ### 5.1 Fick's Laws #### First Law (Flux) $$ J = -D \frac{\partial C}{\partial x} $$ **Where:** - $J$ — flux (atoms/cm²·s) - $D$ — diffusion coefficient (cm²/s) - $C$ — concentration (atoms/cm³) #### Second Law (Time Evolution) $$ \frac{\partial C}{\partial t} = D \frac{\partial^2 C}{\partial x^2} $$ *Assumes constant diffusion coefficient.* #### Diffusion Coefficient Temperature Dependence $$ D = D_0 \exp\left( -\frac{E_a}{kT} \right) $$ ### 5.2 Analytical Solutions #### Constant Surface Concentration (Predeposition) **Boundary conditions:** - $C(0,t) = C_s$ (constant) - $C(\infty,t) = 0$ - $C(x,0) = 0$ **Solution:** $$ C(x,t) = C_s \cdot \text{erfc}\left( \frac{x}{2\sqrt{Dt}} \right) $$ **Total dopant dose:** $$ Q = \frac{2C_s}{\sqrt{\pi}} \cdot \sqrt{Dt} $$ #### Limited Source (Drive-in) **Boundary conditions:** - Total dopant $Q$ conserved - $C(x,0) = Q \cdot \delta(x)$ (delta function) **Solution (Gaussian):** $$ C(x,t) = \frac{Q}{\sqrt{\pi Dt}} \exp\left( -\frac{x^2}{4Dt} \right) $$ #### Junction Depth At the junction, $C(x_j) = C_B$ (background concentration): $$ x_j = 2\sqrt{Dt} \cdot \text{erfc}^{-1}\left( \frac{C_B}{C_s} \right) $$ For Gaussian profile: $$ x_j = 2\sqrt{Dt \cdot \ln\left(\frac{Q}{C_B\sqrt{\pi Dt}}\right)} $$ ### 5.3 Material-Specific Diffusion Parameters #### Silicon | Dopant | $D_0$ (cm²/s) | $E_a$ (eV) | Mechanism | |:-------|:-------------:|:----------:|:----------| | Boron (B) | 0.76 | 3.46 | Interstitialcy | | Phosphorus (P) | 3.85 | 3.66 | Mixed (V + I) | | Arsenic (As) | 22.9 | 4.1 | Vacancy | | Antimony (Sb) | 0.214 | 3.65 | Vacancy | #### Germanium - Higher diffusion coefficients than Si (lower melting point) - B in Ge: $D_0 \approx 1.0$ cm²/s, $E_a \approx 2.5$ eV #### Silicon Carbide - **Extremely low diffusion coefficients** due to strong Si-C bonds - N-type doping (N): $D \approx 10^{-13}$ cm²/s at 1800°C - Implantation is required; diffusion-based doping impractical - Activation requires annealing >1600°C #### GaAs - Si is amphoteric (can be n-type on Ga site, p-type on As site) - Zn diffusion is heavily concentration-dependent - Be is preferred p-type dopant for MBE ## 6. Ion Implantation ### 6.1 Range Distribution — LSS Theory #### Gaussian Approximation $$ C(x) = \frac{\Phi}{\sqrt{2\pi} \Delta R_p} \exp\left( -\frac{(x - R_p)^2}{2 \Delta R_p^2} \right) $$ **Where:** - $\Phi$ — implant dose (ions/cm²) - $R_p$ — projected range (mean depth) (nm) - $\Delta R_p$ — range straggle (standard deviation) (nm) #### Peak Concentration $$ C_{\text{peak}} = \frac{\Phi}{\sqrt{2\pi} \Delta R_p} \approx \frac{0.4 \Phi}{\Delta R_p} $$ ### 6.2 Stopping Power Total energy loss per unit path length: $$ -\frac{dE}{dx} = S_n(E) + S_e(E) $$ **Where:** - $S_n(E)$ — nuclear stopping power (elastic collisions with nuclei) - $S_e(E)$ — electronic stopping power (inelastic electron interactions) #### Nuclear Stopping (Low Energy) Dominant mechanism at low energies. Using ZBL (Ziegler-Biersack-Littmark) potential: $$ S_n \propto \frac{Z_1 Z_2}{(Z_1^{0.23} + Z_2^{0.23})} \cdot \frac{M_1}{M_1 + M_2} $$ **Where:** - $Z_1$, $Z_2$ — atomic numbers of ion and target - $M_1$, $M_2$ — masses of ion and target #### Electronic Stopping (High Energy) $$ S_e \propto Z_1^{1/6} \sqrt{E} $$ At very high energies, Bethe-Bloch formula applies. ### 6.3 Damage and Amorphization #### Displacement Damage — Modified Kinchin-Pease Model $$ N_d = \frac{0.8 \cdot E_d}{2 E_{\text{th}}} $$ **Where:** - $N_d$ — number of displaced atoms per ion - $E_d$ — damage energy deposited (eV) - $E_{\text{th}}$ — threshold displacement energy (eV) - Si: ~15 eV - GaAs: ~10 eV (Ga sublattice), ~9 eV (As sublattice) - SiC: ~20-35 eV #### Critical Dose for Amorphization | Material | Critical Dose (ions/cm²) | Notes | |:---------|:------------------------:|:------| | Si | $10^{14} - 10^{15}$ | Room temperature | | Ge | $10^{13} - 10^{14}$ | Easier to amorphize | | GaAs | $10^{13} - 10^{14}$ | Very easily amorphized | | SiC | $10^{15} - 10^{16}$ | Requires low T or high dose | #### Channeling Effect When ions align with crystal channels, the range increases significantly: $$ R_p^{\text{channeled}} \gg R_p^{\text{random}} $$ Modeling requires Monte Carlo simulations (SRIM/TRIM, Crystal-TRIM). ## 7. Etching ### 7.1 Wet Etching #### Etch Rate Model $$ R = A \exp\left( -\frac{E_a}{kT} \right) [C]^n $$ **Where:** - $R$ — etch rate (nm/min) - $A$ — pre-exponential factor - $[C]$ — etchant concentration - $n$ — reaction order #### Anisotropic Si Etching (KOH, TMAH) Different crystal planes have different bond densities: $$ \frac{R_{\{100\}}}{R_{\{111\}}} \approx 100-400 $$ **Etch selectivity:** $$ S = \frac{R_{\text{material 1}}}{R_{\text{material 2}}} $$ ### 7.2 Reactive Ion Etching (RIE/ICP) #### Ion-Enhanced Etching $$ R_{\text{total}} = R_{\text{chem}} + R_{\text{phys}} + R_{\text{synergy}} $$ The synergy term is typically the largest contribution. #### Child-Langmuir Law for Ion Current $$ J = \frac{4\varepsilon_0}{9} \sqrt{\frac{2e}{M_i}} \cdot \frac{V^{3/2}}{d^2} $$ **Where:** - $J$ — ion current density (A/m²) - $\varepsilon_0$ — vacuum permittivity - $e$ — electron charge - $M_i$ — ion mass (kg) - $V$ — sheath voltage (V) - $d$ — sheath thickness (m) #### Langmuir-Hinshelwood Kinetics (Surface Reaction) $$ R = \frac{k \cdot \theta_A \cdot \theta_B}{(1 + K_A P_A + K_B P_B)^2} $$ **Where:** - $\theta_A$, $\theta_B$ — surface coverage fractions - $K_A$, $K_B$ — adsorption equilibrium constants - $P_A$, $P_B$ — partial pressures ### 7.3 Material-Specific Etching | Material | Wet Etch | Dry Etch | Notes | |:---------|:---------|:---------|:------| | **Si** | KOH, TMAH, HF/HNO₃ | SF₆, CF₄, Cl₂ | Well-established | | **Ge** | H₂O₂/HF | CF₄, SF₆ | Fast etch rates | | **GaAs** | H₂SO₄/H₂O₂, NH₄OH | Cl₂, BCl₃ | Selectivity to AlGaAs | | **SiC** | KOH (molten, 500°C) | SF₆/O₂, ICP | Very slow, needs ICP | ## 8. Lithography ### 8.1 Resolution Limits #### Rayleigh Criterion **Resolution:** $$ R = k_1 \frac{\lambda}{NA} $$ **Depth of Focus:** $$ DOF = k_2 \frac{\lambda}{NA^2} $$ **Where:** - $k_1$ — process factor (0.25–0.8) - $k_2$ — depth of focus factor (~0.5) - $\lambda$ — exposure wavelength (nm) - $NA$ — numerical aperture #### Technology Comparison | Technology | $\lambda$ (nm) | Typical NA | Resolution | |:-----------|:--------------:|:----------:|:-----------| | i-line | 365 | 0.6 | ~350 nm | | KrF | 248 | 0.75 | ~180 nm | | ArF (dry) | 193 | 0.85 | ~90 nm | | ArF (immersion) | 193 | 1.35 | ~38 nm | | EUV | 13.5 | 0.33 | ~13 nm | ### 8.2 Resist Modeling — Dill Parameters #### Absorption in Resist $$ \frac{dI}{dz} = -\alpha(M) \cdot I $$ **Where:** $$ \alpha = A \cdot M + B $$ - $A$ — bleachable absorption coefficient - $B$ — non-bleachable absorption coefficient - $M$ — relative photoactive compound (PAC) concentration #### Exposure Kinetics $$ \frac{dM}{dt} = -C \cdot I \cdot M $$ **Where:** - $C$ — exposure rate constant #### Development Rate (Mack Model) $$ R = R_{\max} \cdot \frac{(a+1)(1-M)^n}{a + (1-M)^n} $$ **Where:** - $R_{\max}$ — maximum development rate - $a$ — selectivity parameter - $n$ — development contrast ## 9. Thin Film Deposition ### 9.1 Physical Vapor Deposition (PVD) #### Sputtering Yield $$ Y = \frac{3\alpha}{4\pi^2} \cdot \frac{4 M_1 M_2}{(M_1 + M_2)^2} \cdot \frac{E}{U_s} $$ **Where:** - $Y$ — sputtering yield (atoms/ion) - $\alpha$ — momentum transfer efficiency - $M_1$, $M_2$ — masses of ion and target atom - $E$ — ion energy (eV) - $U_s$ — surface binding energy (eV) - Si: ~4.7 eV - SiO₂: ~5.0 eV #### Film Thickness Uniformity — Cosine Law $$ \frac{dN}{d\Omega} \propto \cos\theta $$ **Step coverage:** $$ SC = \frac{t_{\text{sidewall}}}{t_{\text{top}}} $$ ### 9.2 Chemical Vapor Deposition (CVD) #### LPCVD Polysilicon from SiH₄ **Reaction:** $$ \text{SiH}_4 \xrightarrow{\Delta} \text{Si} + 2\text{H}_2 $$ **Growth rate:** $$ R = R_0 \exp\left(-\frac{E_a}{kT}\right) \cdot \frac{P_{\text{SiH}_4}}{1 + K_{\text{H}_2} P_{\text{H}_2}} $$ ### 9.3 Atomic Layer Deposition (ALD) **Self-limiting half-reactions:** 1. $\text{Surface-OH} + \text{Al(CH}_3\text{)}_3 \rightarrow \text{Surface-O-Al(CH}_3\text{)}_2 + \text{CH}_4$ 2. $\text{Surface-Al(CH}_3\text{)}_2 + \text{H}_2\text{O} \rightarrow \text{Surface-Al-OH} + 2\text{CH}_4$ **Growth Per Cycle (GPC):** $$ \text{GPC} \approx 0.5 - 1.5 \text{ Å/cycle} $$ Ideal conformal coating with atomic-level thickness control. ## 10. Chemical Mechanical Polishing (CMP) ### 10.1 Preston Equation $$ R = K_p \cdot P \cdot V $$ **Where:** - $R$ — removal rate (nm/min) - $K_p$ — Preston coefficient (material/slurry dependent) - $P$ — applied pressure (Pa) - $V$ — relative velocity (m/s) ### 10.2 Material-Specific CMP | Material | Relative Difficulty | Slurry Type | Notes | |:---------|:-------------------:|:------------|:------| | Si | Low | Colloidal silica | Standard process | | SiO₂ | Low | Ceria, silica | Well-established | | Cu | Medium | Acidic + oxidizer | Dishing/erosion issues | | SiC | **Very High** | Oxidizing, alkaline | Hardness 9.5 Mohs | **SiC CMP challenges:** - Extremely hard material - Tribochemical mechanisms required - Polish times 10-100× longer than Si - Subsurface damage minimization critical ## 11. Process Integration Considerations ### 11.1 Silicon (Si) - **Advantages:** - Mature CMOS technology - Excellent native oxide - Standard processing well-established - **Challenges:** - Scaling limits at sub-3nm nodes - Power density limitations ### 11.2 Germanium (Ge) - **Advantages:** - Higher mobility ($\mu_e$ = 3900, $\mu_h$ = 1900 cm²/V·s) - Compatible with Si processing (mostly) - **Challenges:** - Unstable native oxide → requires passivation (GeO₂/Al₂O₃) - Lower thermal budget (mp = 937°C) - Integration on Si requires graded SiGe buffers ### 11.3 Gallium Arsenide (GaAs) - **Advantages:** - Direct bandgap → optoelectronics - Highest electron mobility (8500 cm²/V·s) - Semi-insulating substrates available - **Challenges:** - No stable native oxide → gate dielectric issues - Surface Fermi level pinning - Stoichiometry control (As overpressure during anneal) - Not used for CMOS (cost, integration) ### 11.4 Silicon Carbide (SiC) - **Advantages:** - Wide bandgap (3.26 eV) → high voltage - High thermal conductivity (4.9 W/cm\cdotK) - High breakdown field (~3 MV/cm) - **Challenges:** - Extreme processing temperatures (>1600°C for activation) - Gate oxide interface quality ($D_{it}$) - Step-controlled epitaxy for polytype control - CMP is very difficult ## 12. TCAD Simulation Framework ### 12.1 Coupled Process Equations Modern process simulation solves coupled PDEs for multiple species: $$ \frac{\partial C_i}{\partial t} = \nabla \cdot (D_i \nabla C_i) + G_i - R_i $$ **Including:** - Dopant diffusion - Point defect dynamics (vacancies $V$, interstitials $I$) - Dopant-defect pairing - Cluster formation and dissolution ### 12.2 Point Defect Mediated Diffusion **Five-stream model:** $$ D_A^{\text{eff}} = D_{AI} \cdot \frac{C_I}{C_I^*} + D_{AV} \cdot \frac{C_V}{C_V^*} $$ **Where:** - $D_{AI}$ — diffusivity via interstitialcy mechanism - $D_{AV}$ — diffusivity via vacancy mechanism - $C_I^*$, $C_V^*$ — equilibrium defect concentrations ### 12.3 Level Set Methods for Topography Interface evolution during etching/deposition: $$ \frac{\partial \phi}{\partial t} + V|\nabla \phi| = 0 $$ **Where:** - $\phi = 0$ defines the interface - $V$ — local etch/deposition rate (can depend on position, orientation) ### 12.4 Monte Carlo Methods **Applications:** - **Ion implantation:** Binary collision approximation (BCA) - SRIM/TRIM for amorphous targets - Crystal-TRIM for channeling effects - **Dopant clustering:** Statistical mechanics of defect formation - **Surface evolution:** Kinetic Monte Carlo for atomic-scale processes ## Physical Constants | Constant | Symbol | Value | |:---------|:------:|:------| | Boltzmann constant | $k$ | $8.617 \times 10^{-5}$ eV/K | | Elementary charge | $e$ | $1.602 \times 10^{-19}$ C | | Vacuum permittivity | $\varepsilon_0$ | $8.854 \times 10^{-12}$ F/m | | Planck constant | $h$ | $6.626 \times 10^{-34}$ J\cdots | | Avogadro number | $N_A$ | $6.022 \times 10^{23}$ mol⁻¹ | ## Unit Conversions | Quantity | Conversion | |:---------|:-----------| | Energy | 1 eV = $1.602 \times 10^{-19}$ J | | Length | 1 Å = $10^{-10}$ m = 0.1 nm | | Temperature | $kT$ at 300 K = 0.0259 eV | | Pressure | 1 Torr = 133.3 Pa |
Shape compound with pressure and heat.
# Semiconductor Manufacturing: Computational Challenges Overview Semiconductor manufacturing represents one of the most mathematically and computationally intensive industrial processes. The complexity stems from multiple scales—from quantum mechanics at atomic level to factory-level logistics. 1. Computational Lithography Mathematical approaches to improve photolithography resolution as features shrink below light wavelength. Key Challenges: • Inverse Lithography Technology (ILT): Treats mask design as inverse problem, solving high-dimensional nonlinear optimization • Optical Proximity Correction (OPC): Solves electromagnetic wave equations with iterative optimization • Source Mask Optimization (SMO): Co-optimizes mask and light source parameters Computational Scale: • Single ILT mask: >10,000 CPU cores for multiple days • GPU acceleration: 40× speedup (500 Hopper GPUs = 40,000 CPU systems) 2. Device Modeling via PDEs Coupled nonlinear partial differential equations model semiconductor devices. Core Equations: Drift-Diffusion System: ∇·(ε∇ψ) = -q(p - n + Nᴅ⁺ - Nₐ⁻) (Poisson) ∂n/∂t = (1/q)∇·Jₙ + G - R (Electron continuity) ∂p/∂t = -(1/q)∇·Jₚ + G - R (Hole continuity) Current densities: Jₙ = qμₙn∇ψ + qDₙ∇n Jₚ = qμₚp∇ψ - qDₚ∇p Numerical Methods: • Finite-difference and finite-element discretization • Newton-Raphson iteration or Gummel's method • Computational meshes for complex geometries 3. CVD Process Simulation CFD models optimize reactor design and operating conditions. Multiscale Modeling: • Nanoscale: DFT and MD for surface chemistry, nucleation, growth • Macroscale: CFD for velocity, pressure, temperature, concentration fields Ab initio quantum chemistry + CFD enables growth rate prediction without extensive calibration. 4. Statistical Process Control SPC distinguishes normal from special variation in production. Key Mathematical Tools: Murphy's Yield Model: Y = [(1 - e⁻ᴰ⁰ᴬ) / D₀A]² Control Charts: • X-bar: UCL = μ + 3σ/√n • EWMA: Zₜ = λxₜ + (1-λ)Zₜ₋₁ Capability Index: Cₚₖ = min[(USL - μ)/3σ, (μ - LSL)/3σ] 5. Production Planning and Scheduling Complexity of multistage production requires advanced optimization. Mathematical Approaches: • Mixed-Integer Programming (MIP) • Variable neighborhood search, genetic algorithms • Discrete event simulation Scale: Managing 55+ equipment units in real-time rescheduling. 6. Level Set Methods Track moving boundaries during etching and deposition. Hamilton-Jacobi equation: ∂ϕ/∂t + F|∇ϕ| = 0 where ϕ is the level set function and F is the interface velocity. Applications: PECVD, ion-milling, photolithography topography evolution. 7. Machine Learning Integration Neural networks applied to: • Accelerate lithography simulation • Predict hotspots (defect-prone patterns) • Optimize mask designs • Model process variations 8. Robust Optimization Addresses yield variability under uncertainty: min max f(x, ξ) x ξ∈U where U is the uncertainty set. Key Computational Bottlenecks • Scale: Thousands of wafers daily, billions of transistors each • Multiphysics: Coupled electromagnetic, thermal, chemical, mechanical phenomena • Multiscale: 12+ orders of magnitude (10⁻¹⁰ m atomic to 10⁻¹ m wafer) • Real-time: Immediate deviation detection and correction • Dimensionality: Millions of optimization variables Summary Computational challenges span: • Numerical PDEs (device simulation) • Optimization theory (lithography, scheduling) • Statistical process control (yield management) • CFD (process simulation) • Quantum chemistry (materials modeling) • Discrete event simulation (factory logistics) The field exemplifies applied mathematics at its most interdisciplinary and impactful.
Image analysis for defect detection.
Measure conductivity at nanoscale.
Different ESD protection levels.
High-resolution 3D imaging.