3,822 technical terms and definitions
step and repeat, lithography scanner, wafer stepper history, ASML scanner, GCA Mark II stepper, exposure field size
Step-and-repeat and step-and-scan are the two fundamentally different ways a lithography tool images a reticle's pattern across a wafer, and the difference between them is exactly…
lithography
A Stepper is a lithography tool that projects a reticle (mask) pattern onto photoresist-coated wafers using a step-and-repeat process — exposing one die (or a small group of dies)…
packaging
Stitch bond is the second wire-bond connection formed by pressing wire onto substrate or lead without forming a free-air ball - it completes the electrical path after the first…
lithography
Stochastic defects are random, unpredictable patterning failures caused by the statistical nature of photoresist chemistry at the nanoscale. Unlike systematic defects (which occur…
stochastic linewidth roughness, euv shot noise lithography
Stochastic edge roughness is the ragged, randomly-varying edge a printed feature gets not from any mechanical imperfection but from counting statistics — too few EUV photons…
lithography
Stochastic Effects in Lithography are random, statistically distributed variations in photon absorption and photochemical reactions in photoresist that produce local pattern…
stokes anti-stokes raman, spontaneous anti-stokes raman, stokes anti-stokes ratio, raman thermometry, anti-stokes thermometry, stokes anti-stokes metrology
Stokes and anti-Stokes Raman bands are mirror-side energy exchanges around the laser line, but they are not automatically mirror images in measured intensity. In Stokes…
raman stress calibration, raman strain calibration, phonon deformation potential calibration, semiconductor stress mapping calibration, spectroscopic stress calibration, stress strain metrology
Stress–strain calibration is the chain that converts a measured spectral or diffraction change into a mechanical quantity with defined units, sign, orientation, spatial weighting…
metrology
Stylus profilometer is a surface measurement instrument that drags a fine-tipped diamond stylus across a surface to measure its topography — providing direct, traceable…
sub-micron features, below one micron, scaling challenges, short-channel effects, DUV lithography
A submicron process is a chip-manufacturing technology generation whose smallest features are below one micrometer, marking the regime the industry entered after crossing…
first silicon success, first silicon, success, working chips, yield rate
Chip Foundry Services achieves 95%+ first-silicon success rate — meaning 95% of our designs work correctly on first fabrication compared to 60-70% industry average, with our…
business
Supply Chain for Chiplets is the multi-vendor ecosystem of design houses, foundries, packaging providers, and test facilities that must coordinate to produce multi-die…
wafer processing optimizing surface activation for direct bonding processes, wafer processing optimizing, processing optimizing surface, optimizing surface activation, wafer processing
Wafer Processing: Optimizing surface activation for direct bonding processes Introduction & Motivation Wafer Processing: Optimizing surface activation for direct bonding processes…
larger contact area lowers mechanical stress bonding, thermal barrier budget independent of contact area, surface barrier cumulative wafer stress remaining margin
Attach the Collector Lead: More Margin on This Face, Less Margin Left in the Wafer This step applies the identical dual constraint step nineteen established — stay under…
metal semiconductor rectifying contact schottky barrier, work function electron affinity barrier height phi_b, surface barrier device name comes from this contact
Electroplate the Collector Into the Bottom Pit: Where This Device's Name Actually Comes From Every junction this project has documented before this step — point-contact's…
stop time mismatch mirror of start time error, diffusion limited residual dissolution after current cutoff, surface barrier two sequential actions current then flush
Halt Etching at Target Base Thickness: Why Stopping Has the Same Timing Problem Starting Did Step fourteen's monitoring circuit detects the moment current reaches , but detecting…
faraday law etch rate current independent circuits, start time offset depth mismatch delta t start, surface barrier timing tolerance shrinks faster etch rate
Initiate Simultaneous Top and Bottom Etching: Why the Two Jets Must Start Together, Not Just Aim Together Step eleven aligned the two jets on a shared point, and step twelve…
shared alignment margin fixture concentricity placement error, usable region defect exclusion zone correct placement, surface barrier as built fixture measurement not nominal tolerance
Position the Wafer Within the Fixture: Spending Step Ten's Margin for the First Time Step eleven built a fixture whose two jets already agree on a shared point in space; this step…
membrane fracture stress force budget rinse, wetting requirement unchanged gentler rinse procedure, surface barrier trading force for time cleaning
Rinse the Etched Wafer: Cleaning a Surface That Can No Longer Absorb a Rough Touch Step nine already established that this process's surfaces have to wet an electrolyte and later…
wafer thickness kerf loss saw cut yield tradeoff, base width ceiling etch pit depth top bottom, surface barrier thickness ceiling spent by etching not firing
Slice the Germanium: The Same Ceiling, Now Approached From Both Faces by Etching Instead of One Pair of Firing Depths Slicing here is the same pure geometry-and-yield problem…
surface barrier transistor, Philco 1953, jet electrolytic etching, electroplated indium, high-frequency germanium transistor, SBT, Tiley and Williams
The surface-barrier transistor is a high-frequency germanium transistor developed at Philco and announced in 1953, in which the active region is made not by melting metal into…
surface barrier transistor electrochemical etching, electroplate metal contacts germanium base thinning, 1953 surface barrier transistor fragile low power, thin base transit time megahertz frequency
The Surface-Barrier Transistor: Jet-Etching a Base Thin Enough to Reach Tens of Megahertz The surface-barrier transistor, introduced by Philco in 1953 (with General Electric…
metrology
Surface Energy Measurement is the quantification of the total intermolecular forces acting at a solid surface by decomposing the surface free energy into its dispersive (van der…
sers, surface enhanced raman scattering, sers spectroscopy, sers enhancement factor, plasmonic raman spectroscopy, sers metrology
A trace residue can produce a spectacular Raman spectrum on one silver nanoparticle junction and disappear a micrometer away, even though the average surface concentration is…
smt, packaging
Surface mount technology is the electronics assembly method where components are mounted directly onto PCB surface pads without through-hole insertion - it is the dominant…
spv, metrology
Surface Photovoltage (SPV) is a non-contact, non-destructive optical metrology technique that measures minority carrier diffusion length and bulk iron concentration in silicon…
sps, metrology
Surface photovoltage spectroscopy (SPS) measures illumination-induced contact potential difference (CPD) change as a function of photon energy. Unlike optical absorption, which…
rca clean, wafer cleaning, surface preparation, sc-1, sc-2, piranha clean, marangoni drying, pre-epi, sc1 sc2, hf last, native oxide, pre-gate, ozone clean
RCA cleaning and advanced semiconductor surface preparation constitute the sequential wet chemical and physical processes engineered to remove organic residues, sub-micron…
advanced packaging
Surface Preparation for Bonding is the critical set of cleaning, planarization, and activation steps that determine whether wafer bonding succeeds or fails — because direct…
metrology
Surface Roughness Measurement in semiconductor manufacturing is the quantitative characterization of surface height variations at various spatial scales — using a combination…
surface roughness metrology drift prediction machine learning, surface roughness, metrology drift prediction, surface roughness metrology drift prediction, metrology drift
Surface Roughness Metrology Drift Prediction with Machine Learning Introduction & Motivation Surface Roughness Metrology Drift Prediction with Machine Learning addresses a central…
metamodel chip design, response surface methodology, kriging surrogate eda, model based optimization
Surrogate Modeling for Optimization is the technique of constructing fast-to-evaluate approximations (surrogates or metamodels) of expensive chip design objectives and constraints…
wafer susceptor, cvd susceptor, epitaxial susceptor, graphite susceptor
The wafer susceptor serves as the primary thermal reservoir, mechanical support, and gas-dynamic substrate holder in semiconductor chemical vapor deposition (CVD), metal-organic…
synchrotron x-ray metrology, synchrotron radiation methods, synchrotron semiconductor characterization, synchrotron beamline techniques, coherent x-ray methods, operando synchrotron x-ray
Synchrotron X-ray techniques use radiation emitted by relativistic electrons circulating through magnetic structures and delivered to specialized beamlines. Compared with a fixed…
system-in-package, SiP, multichip module, heterogeneous package
System in package. integrates multiple semiconductor dies and often passives, sensors, filters, antennas, or power devices inside one package boundary. Unlike a monolithic system…
logic design predicting defect propagation in system-on-chip (soc) integration from module-level data, logic design predicting, design predicting defect, predicting defect propagation
Logic Design: Predicting defect propagation in system-on-chip (SoC) integration from module-level data Introduction & Motivation Logic Design: Predicting defect propagation…
system-on-chip power budget breakdown prediction, system-on-chip power budget, power budget breakdown, budget breakdown prediction, system-on-chip power, power budget
System-on-Chip Power Budget Breakdown Prediction with Machine Learning Introduction & Motivation System-on-Chip Power Budget Breakdown Prediction with Machine Learning addresses…
soc, system-on-chip, heterogeneous soc, cpu gpu npu soc, soc architecture, soc design
System on chip integrates processors, accelerators, memory control, interconnect, security, I/O and often analog or RF functions on one die or tightly coupled package. SoCs…
metrology
Systematic defects are repeating, predictable defect patterns — caused by process issues, equipment problems, or design weaknesses that create consistent failures, as opposed…
metrology
Spectroscopic ellipsometry and inline optical wafer metrology constitute the non-destructive physical measurement and defect detection disciplines that govern yield control across…
tape and reel packaging quality and pull force prediction with machine learning, tape reel packaging quality pull force prediction machine learning, tape reel
Tape and Reel Packaging Quality and Pull-Force Prediction with Machine Learning Introduction & Motivation Tape and Reel Packaging Quality and Pull-Force Prediction with Machine…
gdsii, foundry, sign-off, verification, fabrication
Tape-out is the moment a completed chip layout leaves the design team and becomes a manufacturing order at the foundry. It is a technical checkpoint and a business commitment.…
packaging
Tape width is the overall width of carrier tape used to package electronic components for feeder compatibility and pocket sizing - it determines which feeder hardware can run…
tapeout signoff, gdsii signoff, chip tapeout flow, final signoff checklist
Tapeout Methodology and Signoff is the rigorous multi-step verification and validation process that a chip design must pass before the final GDS-II layout data is released to…
tarc, top arc, top anti-reflective coating, top antireflective coating, swing curve suppression, immersion topcoat, lithography
Top anti-reflective coating is a thin, transparent fluoropolymer or water-soluble organic film applied directly onto the top surface of a photoresist layer prior to lithographic…
technology cad, sentaurus, silvaco, scharfetter gummel, mesh convergence, band gap narrowing, tcad calibration, device tcad, process tcad, tcad modeling, semiconductor device modeling
Technology computer-aided design solves the semiconductor device equations — Poisson's equation coupled to the electron and hole continuity equations — on a discrete mesh, and its…
tem, transmission electron microscopy, metrology
Transmission electron microscopy (TEM) provides sub-angstrom resolution imaging of semiconductor device cross-sections, enabling atomic-level characterization of transistor…
high-temperature bake, packaging, thermal process
High-temperature bake is the shorter-duration moisture-removal process using elevated temperatures for rapid drying of qualified packages - it is used when components and carriers…
on die thermal sensor, thermal diode, thermal management chip, pvt monitor
On-Die Temperature Sensors and PVT Monitors are the integrated measurement circuits distributed across the chip that continuously monitor die temperature, supply voltage…
advanced packaging
Temporary Bonding is a reversible wafer bonding process that attaches a device wafer to a rigid carrier wafer using a removable adhesive — providing mechanical support during…