hbm (high bandwidth memory),hbm,high bandwidth memory,advanced packaging
Stacked memory with wide interface for high bandwidth.
923 technical terms and definitions
Stacked memory with wide interface for high bandwidth.
Second generation HBM.
Third generation with higher bandwidth.
Measure vertical dimensions.
Create airtight seal.
Combine different technologies in one package.
Combine dies from different technologies or materials in one package.
Stacked DRAM with wide interface.
Z-contrast imaging in STEM.
Higher numerical aperture for better resolution.
Overlay beyond simple X-Y shift (rotation scaling).
Faster moisture removal.
Lead-free requires higher temp.
# Sam Zeloof and the Mathematics of DIY Semiconductor Fabrication ## Table of Contents ## The Remarkable Story Sam Zeloof represents something extraordinary in the semiconductor world: a self-taught engineer who, starting at age 17 in 2016, built a functional chip fabrication facility in his parents' New Jersey garage—located about 30 miles from Bell Labs, where the first transistor was created in 1947. ### Timeline of Achievements - **2016**: Started experimenting with semiconductor fabrication at age 17 - **2017**: Successfully replicated Jeri Ellsworth's homemade transistors - **2018**: Produced the **Z1 chip** (first homebrew lithographically fabricated IC) - 6 transistors - PMOS dual differential amplifier - 175μm feature size - **2021**: Created the **Z2 chip** - 1,200 transistors (12 arrays of 100 transistors each) - 10μm polysilicon gate process - Same technology as Intel's first CPU (4004) - Threshold voltage: $V_{th} = 1.1V$ - Leakage current: $I_{leak} = 59nA$ - **2022**: Co-founded **Atomic Semi** with Jim Keller - **Present**: Photolithography resolution down to ~300nm ### Key Equipment (Salvaged/Homemade) - Modified digital projector with microscope optical stage for photolithography - Repaired electron microscope (purchased broken for $1,000) - Homemade vacuum chamber from surplus parts - Chemistry bench for wet processing - Fiber laser for wafer scribing ## Device Physics: Fundamental Semiconductor Equations The behavior of semiconductor devices is governed by a coupled system of partial differential equations describing electrostatic potential, carrier concentrations, and current flow. ### Poisson's Equation Describes the electrostatic potential distribution: $$ \nabla \cdot (\epsilon \nabla \psi) = -q(p - n + N_D^+ - N_A^-) $$ **Where:** - $\psi$ = electrostatic potential (V) - $\epsilon$ = permittivity (F/cm) - $q$ = elementary charge ($1.6 \times 10^{-19}$ C) - $p$ = hole concentration (cm⁻³) - $n$ = electron concentration (cm⁻³) - $N_D^+$ = ionized donor concentration (cm⁻³) - $N_A^-$ = ionized acceptor concentration (cm⁻³) ### Continuity Equations Describe carrier transport and conservation: **For electrons:** $$ \frac{\partial n}{\partial t} = \frac{1}{q}\nabla \cdot \vec{J}_n - R $$ **For holes:** $$ \frac{\partial p}{\partial t} = -\frac{1}{q}\nabla \cdot \vec{J}_p - R $$ **Where:** - $\vec{J}_n$, $\vec{J}_p$ = electron and hole current densities (A/cm²) - $R$ = net recombination rate (cm⁻³s⁻¹) ### Drift-Diffusion Current Relations **Electron current density:** $$ \vec{J}_n = q\mu_n n\vec{E} + qD_n\nabla n $$ **Hole current density:** $$ \vec{J}_p = q\mu_p p\vec{E} - qD_p\nabla p $$ **Where:** - $\mu_n$, $\mu_p$ = electron and hole mobilities (cm²/V·s) - $D_n$, $D_p$ = diffusion coefficients (cm²/s) - $\vec{E}$ = electric field (V/cm) **Einstein Relation** (connects mobility and diffusion): $$ D = \frac{kT}{q}\mu $$ ## MOSFET Device Equations Zeloof's PMOS transistors follow the classic MOSFET equations. ### Operating Regions #### 1. Cutoff Region $$ V_{GS} < V_T \quad \Rightarrow \quad I_{DS} \approx 0 $$ #### 2. Linear (Triode) Region **Condition:** $V_{GS} > V_T$ and $V_{DS} < V_{GS} - V_T$ $$ I_{DS} = \mu_n C_{ox} \frac{W}{L} \left[ (V_{GS} - V_T)V_{DS} - \frac{V_{DS}^2}{2} \right] $$ #### 3. Saturation Region **Condition:** $V_{GS} > V_T$ and $V_{DS} \geq V_{GS} - V_T$ $$ I_{DS} = \frac{1}{2}\mu_n C_{ox}\frac{W}{L}(V_{GS} - V_T)^2(1 + \lambda V_{DS}) $$ ### Parameter Definitions | Parameter | Symbol | Description | Units | |-----------|--------|-------------|-------| | Threshold voltage | $V_T$ | Gate voltage for channel formation | V | | Oxide capacitance | $C_{ox}$ | Gate oxide capacitance per area | F/cm² | | Channel width | $W$ | Transistor width | μm | | Channel length | $L$ | Transistor length | μm | | Channel length modulation | $\lambda$ | Output conductance parameter | V⁻¹ | ### Oxide Capacitance $$ C_{ox} = \frac{\epsilon_{ox}}{t_{ox}} = \frac{K_{ox} \epsilon_0}{t_{ox}} $$ **Where:** - $\epsilon_{ox}$ = oxide permittivity - $t_{ox}$ = oxide thickness - $K_{ox} \approx 3.9$ for SiO₂ - $\epsilon_0 = 8.854 \times 10^{-14}$ F/cm ### Threshold Voltage $$ V_T = V_{FB} + 2\phi_F + \frac{\sqrt{2\epsilon_{Si}qN_A(2\phi_F)}}{C_{ox}} $$ **Where:** - $V_{FB}$ = flat-band voltage - $\phi_F$ = Fermi potential - $N_A$ = acceptor doping concentration ### Transconductance $$ g_m = \frac{\partial I_{DS}}{\partial V_{GS}} = \mu_n C_{ox} \frac{W}{L}(V_{GS} - V_T) $$ In saturation: $$ g_m = \sqrt{2\mu_n C_{ox}\frac{W}{L}I_{DS}} $$ ### Subthreshold Current Below threshold, current varies exponentially: $$ I_{DS} = I_{D0} \exp\left(\frac{V_{GS} - V_T}{nV_T}\right)\left(1 - \exp\left(-\frac{V_{DS}}{V_T}\right)\right) $$ **Subthreshold slope:** $$ S = n \cdot \frac{kT}{q} \cdot \ln(10) \approx 60-100 \text{ mV/decade at room temperature} $$ ## Diffusion: Fick's Laws The doping process relies on thermal diffusion of impurities into silicon. ### Fick's First Law Describes the flux of diffusing species: $$ J = -D\frac{\partial C}{\partial x} $$ **Where:** - $J$ = flux (atoms/cm²·s) - $D$ = diffusion coefficient (cm²/s) - $C$ = concentration (atoms/cm³) ### Fick's Second Law Describes time-dependent concentration profile: $$ \frac{\partial C}{\partial t} = D\frac{\partial^2 C}{\partial x^2} $$ For one dimension with constant $D$. ### Temperature Dependence of Diffusion Coefficient Follows Arrhenius behavior: $$ D = D_0 \exp\left(-\frac{E_a}{kT}\right) $$ **Where:** - $D_0$ = pre-exponential factor (cm²/s) - $E_a$ = activation energy (eV) - $k$ = Boltzmann constant ($8.617 \times 10^{-5}$ eV/K) - $T$ = absolute temperature (K) ### Diffusion Profile Solutions #### 1. Constant Surface Concentration (Predeposition) **Boundary conditions:** - $C(0,t) = C_s$ (surface concentration constant) - $C(\infty,t) = 0$ - $C(x,0) = 0$ **Solution:** $$ C(x,t) = C_s \cdot \text{erfc}\left(\frac{x}{2\sqrt{Dt}}\right) $$ **Where erfc is the complementary error function:** $$ \text{erfc}(z) = 1 - \text{erf}(z) = 1 - \frac{2}{\sqrt{\pi}}\int_0^z e^{-t^2}dt $$ **Total dose:** $$ Q(t) = \frac{2C_s\sqrt{Dt}}{\sqrt{\pi}} $$ #### 2. Constant Total Dopant (Drive-in) **Boundary conditions:** - Total dopant $Q$ is fixed - $\int_0^\infty C(x,t)dx = Q$ **Solution (Gaussian profile):** $$ C(x,t) = \frac{Q}{\sqrt{\pi Dt}}\exp\left(-\frac{x^2}{4Dt}\right) $$ **Junction depth** (where $C(x_j) = C_B$, background concentration): $$ x_j = 2\sqrt{Dt \cdot \ln\left(\frac{Q}{C_B\sqrt{\pi Dt}}\right)} $$ ### Diffusion Coefficients for Common Dopants in Silicon | Dopant | $D_0$ (cm²/s) | $E_a$ (eV) | Type | |--------|---------------|------------|------| | Boron | 10.5 | 3.69 | p-type | | Phosphorus | 10.5 | 3.69 | n-type | | Arsenic | 0.32 | 3.56 | n-type | | Antimony | 5.6 | 3.95 | n-type | ## Oxidation Kinetics: Deal-Grove Model Zeloof grows gate oxide layers through thermal oxidation of silicon. ### Chemical Reaction $$ \text{Si} + \text{O}_2 \rightarrow \text{SiO}_2 \quad \text{(dry oxidation)} $$ $$ \text{Si} + 2\text{H}_2\text{O} \rightarrow \text{SiO}_2 + 2\text{H}_2 \quad \text{(wet oxidation)} $$ ### Deal-Grove Equation $$ x_{ox}^2 + Ax_{ox} = B(t + \tau) $$ **Where:** - $x_{ox}$ = oxide thickness - $A$, $B$ = temperature-dependent constants - $\tau$ = accounts for initial oxide - $t$ = oxidation time ### Limiting Cases #### Linear Regime (thin oxides, $x_{ox} \ll A$): $$ x_{ox} \approx \frac{B}{A}(t + \tau) $$ Rate coefficient: $B/A$ (linear rate constant) #### Parabolic Regime (thick oxides, $x_{ox} \gg A$): $$ x_{ox} \approx \sqrt{B(t + \tau)} $$ Rate coefficient: $B$ (parabolic rate constant) ### Explicit Solution $$ x_{ox} = \frac{A}{2}\left(\sqrt{1 + \frac{4B(t+\tau)}{A^2}} - 1\right) $$ ### Rate Constants (Typical Values at 1000°C) | Parameter | Dry O₂ | Wet O₂ | |-----------|--------|--------| | $B/A$ (μm/hr) | 0.165 | 1.31 | | $B$ (μm²/hr) | 0.0117 | 0.287 | ## Photolithography Resolution Zeloof uses a modified digital projector with a microscope optical stage. ### Rayleigh Criterion Minimum resolvable feature size: $$ \text{Resolution} = k_1 \frac{\lambda}{NA} $$ **Where:** - $k_1$ = process-dependent factor (0.25–0.8) - $\lambda$ = wavelength of light - $NA$ = numerical aperture ### Depth of Focus $$ DOF = k_2 \frac{\lambda}{NA^2} $$ ### Numerical Aperture $$ NA = n \sin(\theta) $$ **Where:** - $n$ = refractive index of medium - $\theta$ = half-angle of light cone ### Zeloof's System Performance - **Light source:** UV from modified projector - **Theoretical resolution:** ~1 μm - **Practical resolution (without cleanroom):** ~10 μm - **Current capability:** ~300 nm ### Exposure Dose $$ E = I \cdot t $$ **Where:** - $E$ = exposure energy (mJ/cm²) - $I$ = intensity (mW/cm²) - $t$ = exposure time (s) ## Moore's Law: Exponential Growth Model ### Mathematical Formulation $$ N(t) = N_0 \cdot 2^{t/\tau} $$ **Where:** - $N(t)$ = transistor count at time $t$ - $N_0$ = initial transistor count - $\tau$ = doubling time (~2 years historically) ### Logarithmic Form $$ \log_2(N) = \log_2(N_0) + \frac{t}{\tau} $$ A straight line on a semi-log plot indicates exponential growth. ### Historical Data | Year | Processor | Transistors | |------|-----------|-------------| | 1971 | Intel 4004 | 2,308 | | 1978 | Intel 8086 | 29,000 | | 1989 | Intel 486 | 1,180,000 | | 2000 | Pentium 4 | 42,000,000 | | 2021 | Apple M1 Max | 57,000,000,000 | | 2025 | NVIDIA GB202 | 92,200,000,000 | ### Zeloof's Personal Moore's Law - **Z1 (2018):** 6 transistors - **Z2 (2021):** 1,200 transistors - **Growth factor:** 200× in ~3 years **Calculating doubling time:** $$ 1200 = 6 \cdot 2^{3/\tau} $$ $$ 200 = 2^{3/\tau} $$ $$ \log_2(200) = \frac{3}{\tau} $$ $$ \tau = \frac{3}{\log_2(200)} = \frac{3}{7.64} \approx 0.39 \text{ years} \approx 5 \text{ months} $$ **Zeloof's doubling time (~5 months) dramatically exceeds the industry standard (~24 months)!** ### Dennard Scaling (Related) As transistors shrink by factor $\kappa$: | Parameter | Scaling | |-----------|---------| | Dimension | $1/\kappa$ | | Voltage | $1/\kappa$ | | Current | $1/\kappa$ | | Delay | $1/\kappa$ | | Power | $1/\kappa^2$ | | Power density | constant | ## Yield Modeling ### Poisson Model (Simple) $$ Y = e^{-AD} $$ **Where:** - $Y$ = yield (fraction of working chips) - $A$ = chip area (cm²) - $D$ = defect density (defects/cm²) ### Murphy's Model (More Realistic) $$ Y = \left(\frac{1 - e^{-AD}}{AD}\right)^2 $$ ### Seeds Model $$ Y = e^{-\sqrt{AD}} $$ ### Zeloof's Yield - **Reported yield:** Up to 80% for large features - **Key factors:** - No cleanroom (increases defect density) - Large feature sizes (increases tolerance) - Small die area (improves yield per chip) - Manual processing (introduces variability) ## Hierarchy of Semiconductor Models ### Level 1: Quantum Models **Schrödinger Equation:** $$ i\hbar\frac{\partial\Psi}{\partial t} = -\frac{\hbar^2}{2m^*}\nabla^2\Psi + V\Psi $$ **Where:** - $\Psi$ = wave function - $\hbar$ = reduced Planck constant - $m^*$ = effective mass - $V$ = potential energy **Applications:** - Tunneling phenomena - Quantum confinement - Band structure calculations ### Level 2: Kinetic Models **Boltzmann Transport Equation:** $$ \frac{\partial f}{\partial t} + \vec{v}\cdot\nabla_r f + \frac{q\vec{E}}{m^*}\cdot\nabla_k f = \left(\frac{\partial f}{\partial t}\right)_{\text{coll}} $$ **Where:** - $f$ = distribution function - $\vec{v}$ = velocity - $\vec{k}$ = wave vector **Applications:** - Hot carrier effects - Non-equilibrium transport - Monte Carlo simulations ### Level 3: Macroscopic Models **Drift-Diffusion Equations** (as described above) **Applications:** - Standard device simulation - Circuit modeling - TCAD tools ### Model Selection Criteria | Model | Speed | Accuracy | Feature Size | |-------|-------|----------|--------------| | Drift-Diffusion | Fast | Good for >50nm | >50 nm | | Energy Balance | Medium | Better | 20-50 nm | | Monte Carlo | Slow | Excellent | <20 nm | | Quantum | Very Slow | Required | <10 nm | ## Atomic Semi: From Garage to Startup ### Company Overview - **Founded:** 2022 - **Co-founders:** Sam Zeloof (CEO) and Jim Keller - **Location:** San Francisco, CA - **Mission:** Build small, fast semiconductor fabs ### Vision - Create fab equipment "like ASML" but smaller scale - Target smaller chips instead of 300mm wafers - Enable rapid prototyping (hours instead of months) - Democratize chip manufacturing ### Investment Interest - OpenAI Startup Fund (seed round discussions) - Valuation: ~$100 million - Notable interested investors: - Fred Ehrsam (Paradigm founder) - Nat Friedman (former GitHub CEO) - Naval Ravikant ### Technical Approach - Miniaturized fab equipment - Custom tooling development - Pushing toward advanced geometries - Focus on small-batch production ## Key Takeaways ### 1. Democratization of Innovation > "That really high barrier to entry will make you super risk-averse, and that's bad for innovation." > — Sam Zeloof The mathematical frameworks underlying chip fabrication aren't secret—they're well-documented physics accessible to anyone willing to learn. ### 2. Scaling Laws Apply at All Levels Whether you're Intel with $100 billion or Zeloof with salvaged equipment, the same equations govern device behavior: - Poisson's equation for electrostatics - Drift-diffusion for current flow - Fick's laws for doping - Deal-Grove for oxidation ### 3. Mathematical Foundation Required Success in semiconductor fabrication requires understanding: - **Partial differential equations** (device physics) - **Error functions and Gaussians** (diffusion profiles) - **Exponential kinetics** (oxidation, diffusion coefficients) - **Statistical models** (yield prediction) - **Optical physics** (lithography resolution) ### 4. Exponential Learning Possible Zeloof's transistor count growth demonstrates that rapid iteration with immediate feedback can produce remarkable scaling—even faster than Moore's Law. ### 5. Historical Perspective The semiconductor revolution started with individuals tinkering in labs. Zeloof's work proves that with sufficient mathematical understanding, creativity, and persistence, the fundamental tools of modern technology can be recreated outside the corporate-industrial complex. ## Physical Constants | Constant | Symbol | Value | Units | |----------|--------|-------|-------| | Elementary charge | $q$ | $1.602 \times 10^{-19}$ | C | | Boltzmann constant | $k$ | $8.617 \times 10^{-5}$ | eV/K | | Planck constant | $h$ | $6.626 \times 10^{-34}$ | J·s | | Vacuum permittivity | $\epsilon_0$ | $8.854 \times 10^{-14}$ | F/cm | | Thermal voltage (300K) | $V_T = kT/q$ | 0.0259 | V | | Intrinsic carrier conc. (Si, 300K) | $n_i$ | $1.5 \times 10^{10}$ | cm⁻³ | | Silicon permittivity | $\epsilon_{Si}$ | $1.04 \times 10^{-12}$ | F/cm | | SiO₂ permittivity | $\epsilon_{ox}$ | $3.45 \times 10^{-13}$ | F/cm |
# Jeri Ellsworth's Homemade Transistors: The Mathematics Behind DIY Semiconductor Manufacturing ## 1. The Pioneer and Her Process **Jeri Ellsworth** is an American entrepreneur and autodidact computer chip designer who demonstrated that functional transistors can be fabricated in a home laboratory setting. ### Key Facts: - **Timeline**: Built home-based fabrication facility in 2010 - **Development Time**: Approximately 2 years to perfect the process - **Achievement**: Successfully created working N-channel FETs - **Scale**: Transistors measured in inches (not micrometers) - **Method**: Single transistor fabrication at a time ### Materials Used: | Component | Source | |-----------|--------| | Silicon Wafers | eBay (p-doped) | | Acid Source | Store-bought rust remover | | Deionized Water | Aquafina (crude substitute) | | Etchant | Hydrofluoric acid (HF) | | Dopant | Phosphosilicate glass | | Masks | Vinyl stickers (cut with vinyl cutter) | ## 2. The Fabrication Process ### 2.1 Process Flow ``` - ┌─────────────────┐ │ Silicon Wafer │ │ (p-doped) │ └────────┬────────┘ │ ▼ ┌─────────────────┐ │ Thermal Oxide │ │ Growth │ │ (500-600 Å) │ └────────┬────────┘ │ ▼ ┌─────────────────┐ │ Vinyl Mask │ │ Application │ └────────┬────────┘ │ ▼ ┌─────────────────┐ │ HF Etching │ │ (Pattern Oxide)│ └────────┬────────┘ │ ▼ ┌─────────────────┐ │ Doping │ │ (Phosphosilicate│ │ Spin-on) │ └────────┬────────┘ │ ▼ ┌─────────────────┐ │ Gate Oxide │ │ Growth │ │ (800-1000 Å) │ └────────┬────────┘ │ ▼ ┌─────────────────┐ │ Contacts │ │(Conductive Epoxy│ └─────────────────┘ ``` ### 2.2 Critical Parameters - **Field Oxide Thickness**: 500-600 Å (green color indicator) - **Gate Oxide Thickness**: 800-1000 Å (pink to dark red color) - **Furnace Temperature**: ~1000°C - **Oxide Growth Time**: ~6 hours with steam ### 2.3 Color-Thickness Correlation | Oxide Thickness (Å) | Observed Color | |---------------------|----------------| | 500-600 | Green | | 800-1000 | Pink to Dark Red | | 1000-1200 | Blue | | 1500-2000 | Gold/Yellow | ## 3. Mathematical Models ### 3.1 Deal-Grove Oxidation Model The **Deal-Grove model** (1965) mathematically describes thermal oxide growth on silicon surfaces. #### 3.1.1 Fundamental Equation $$ x^2 + Ax = B(t + \tau) $$ **Where:** - $x$ = oxide thickness (cm or nm) - $t$ = oxidation time (seconds or minutes) - $A$ = linear rate constant parameter (cm) - $B$ = parabolic rate constant (cm²/s) - $\tau$ = time offset for initial oxide #### 3.1.2 Explicit Solution for Oxide Thickness $$ x(t) = \frac{A}{2}\left(\sqrt{1 + \frac{4B}{A^2}(t + \tau)} - 1\right) $$ #### 3.1.3 Rate Constants The constants $A$ and $B$ are defined as: $$ A = 2D_{ox}\left(\frac{1}{k_s} + \frac{1}{h_g}\right) $$ $$ B = \frac{2D_{ox}C_g}{N} $$ $$ \tau = \frac{x_i^2 + Ax_i}{B} $$ **Where:** - $D_{ox}$ = diffusivity of oxidant in oxide (cm²/s) - $k_s$ = surface reaction rate constant (cm/s) - $h_g$ = gas-phase transport coefficient (cm/s) - $C_g$ = equilibrium oxidant concentration in gas - $N$ = number of oxidant molecules per unit volume of oxide - $x_i$ = initial oxide thickness #### 3.1.4 Limiting Cases **Linear Regime** (thin oxide, short times): When $t + \tau \ll \frac{A^2}{4B}$: $$ x(t) \approx \frac{B}{A}(t + \tau) $$ - Growth rate is **reaction-limited** - Oxide thickness grows linearly with time - Applies to Ellsworth's initial oxide growth **Parabolic Regime** (thick oxide, long times): When $t + \tau \gg \frac{A^2}{4B}$: $$ x(t) \approx \sqrt{B(t + \tau)} $$ - Growth rate is **diffusion-limited** - Oxide thickness grows with square root of time - Applies to Ellsworth's longer oxidation cycles #### 3.1.5 Temperature Dependence The rate constants follow Arrhenius behavior: $$ \frac{B}{A} = C_1 \exp\left(-\frac{E_{a1}}{k_B T}\right) $$ $$ B = C_2 \exp\left(-\frac{E_{a2}}{k_B T}\right) $$ **Where:** - $E_{a1}$ = activation energy for linear rate (~2.0 eV for dry O₂) - $E_{a2}$ = activation energy for parabolic rate (~1.2 eV for dry O₂) - $k_B$ = Boltzmann constant ($8.617 \times 10^{-5}$ eV/K) - $T$ = absolute temperature (K) #### 3.1.6 Wet vs. Dry Oxidation | Parameter | Dry O₂ | Wet (H₂O) | |-----------|--------|-----------| | $B/A$ at 1000°C | 0.0117 μm/hr | 0.226 μm/hr | | $B$ at 1000°C | 0.0011 μm²/hr | 0.287 μm²/hr | | Quality | Higher | Lower | | Growth Rate | Slower | Faster | **Chemical Reactions:** Dry oxidation: $$ \text{Si} + \text{O}_2 \rightarrow \text{SiO}_2 \quad (\Delta H \approx -7.36 \text{ eV/atom}) $$ Wet oxidation: $$ \text{Si} + 2\text{H}_2\text{O} \rightarrow \text{SiO}_2 + 2\text{H}_2 $$ ### 3.2 Fick's Laws of Diffusion Dopant distribution in the source/drain regions follows **Fick's laws**. #### 3.2.1 Fick's First Law $$ J = -D\frac{\partial C}{\partial x} $$ **Where:** - $J$ = diffusion flux (atoms/cm²·s) - $D$ = diffusion coefficient (cm²/s) - $C$ = concentration (atoms/cm³) - $x$ = position (cm) #### 3.2.2 Fick's Second Law $$ \frac{\partial C}{\partial t} = D\frac{\partial^2 C}{\partial x^2} $$ For **concentration-dependent diffusion**: $$ \frac{\partial C}{\partial t} = \frac{\partial}{\partial x}\left(D(C)\frac{\partial C}{\partial x}\right) $$ #### 3.2.3 Diffusion Coefficient Temperature Dependence $$ D = D_0 \exp\left(-\frac{E_a}{k_B T}\right) $$ **Typical Values for Silicon:** | Dopant | $D_0$ (cm²/s) | $E_a$ (eV) | $D$ at 1000°C (cm²/s) | |--------|---------------|------------|----------------------| | Phosphorus (P) | 10.5 | 3.69 | $2.5 \times 10^{-14}$ | | Boron (B) | 10.5 | 3.69 | $2.0 \times 10^{-14}$ | | Arsenic (As) | 0.32 | 3.56 | $1.2 \times 10^{-15}$ | | Antimony (Sb) | 5.6 | 3.95 | $1.0 \times 10^{-15}$ | #### 3.2.4 Solution: Constant Surface Concentration **Boundary Conditions:** - $C(0,t) = C_s$ (constant surface concentration) - $C(x,0) = 0$ (initially undoped) - $C(\infty,t) = 0$ (bulk remains undoped) **Solution:** $$ C(x,t) = C_s \cdot \text{erfc}\left(\frac{x}{2\sqrt{Dt}}\right) $$ **Where erfc is the complementary error function:** $$ \text{erfc}(z) = 1 - \text{erf}(z) = 1 - \frac{2}{\sqrt{\pi}}\int_0^z e^{-u^2}du $$ **Total Dopant per Unit Area:** $$ Q(t) = \int_0^\infty C(x,t)dx = \frac{2C_s\sqrt{Dt}}{\sqrt{\pi}} $$ #### 3.2.5 Solution: Limited Source (Gaussian) **Boundary Conditions:** - Initial dose $Q_0$ deposited at surface - $\int_0^\infty C(x,t)dx = Q_0$ (conservation) **Solution:** $$ C(x,t) = \frac{Q_0}{\sqrt{\pi Dt}} \exp\left(-\frac{x^2}{4Dt}\right) $$ **Peak Concentration (at surface):** $$ C_{max} = C(0,t) = \frac{Q_0}{\sqrt{\pi Dt}} $$ **Characteristic Diffusion Length:** $$ L_D = 2\sqrt{Dt} $$ #### 3.2.6 Junction Depth Calculation For a p-n junction formed by diffusion into oppositely doped substrate: **erfc profile:** $$ x_j = 2\sqrt{Dt} \cdot \text{erfc}^{-1}\left(\frac{C_B}{C_s}\right) $$ **Gaussian profile:** $$ x_j = 2\sqrt{Dt \cdot \ln\left(\frac{Q_0}{C_B\sqrt{\pi Dt}}\right)} $$ **Where:** - $x_j$ = junction depth - $C_B$ = background doping concentration ### 3.3 Drift-Diffusion Equations The **drift-diffusion model** describes carrier transport in semiconductor devices. #### 3.3.1 Poisson's Equation $$ \nabla^2 \phi = -\frac{\rho}{\epsilon} = -\frac{q}{\epsilon}\left(p - n + N_D^+ - N_A^-\right) $$ **Where:** - $\phi$ = electrostatic potential (V) - $\rho$ = charge density (C/cm³) - $\epsilon$ = permittivity ($\epsilon_{Si} = 11.7\epsilon_0$) - $q$ = elementary charge ($1.602 \times 10^{-19}$ C) - $n$ = electron concentration (cm⁻³) - $p$ = hole concentration (cm⁻³) - $N_D^+$ = ionized donor concentration (cm⁻³) - $N_A^-$ = ionized acceptor concentration (cm⁻³) #### 3.3.2 Continuity Equations **For electrons:** $$ \frac{\partial n}{\partial t} = \frac{1}{q}\nabla \cdot \vec{J}_n + G_n - R_n $$ **For holes:** $$ \frac{\partial p}{\partial t} = -\frac{1}{q}\nabla \cdot \vec{J}_p + G_p - R_p $$ **Where:** - $\vec{J}_n$, $\vec{J}_p$ = current densities (A/cm²) - $G_n$, $G_p$ = generation rates (cm⁻³s⁻¹) - $R_n$, $R_p$ = recombination rates (cm⁻³s⁻¹) #### 3.3.3 Current Density Equations **Electron current (drift + diffusion):** $$ \vec{J}_n = q\mu_n n \vec{E} + qD_n \nabla n $$ $$ \vec{J}_n = qn\mu_n\nabla\phi + qD_n\nabla n $$ **Hole current (drift + diffusion):** $$ \vec{J}_p = q\mu_p p \vec{E} - qD_p \nabla p $$ $$ \vec{J}_p = -qp\mu_p\nabla\phi - qD_p\nabla p $$ **Where:** - $\mu_n$, $\mu_p$ = carrier mobilities (cm²/V·s) - $D_n$, $D_p$ = diffusion coefficients (cm²/s) - $\vec{E} = -\nabla\phi$ = electric field (V/cm) #### 3.3.4 Einstein Relation $$ D_n = \frac{k_B T}{q}\mu_n = V_T \mu_n $$ $$ D_p = \frac{k_B T}{q}\mu_p = V_T \mu_p $$ **Where:** - $V_T = \frac{k_B T}{q}$ = thermal voltage - At $T = 300$ K: $V_T \approx 25.9$ mV #### 3.3.5 Recombination Models **Shockley-Read-Hall (SRH) Recombination:** $$ R_{SRH} = \frac{np - n_i^2}{\tau_p(n + n_1) + \tau_n(p + p_1)} $$ **Auger Recombination:** $$ R_{Auger} = C_n n(np - n_i^2) + C_p p(np - n_i^2) $$ **Where:** - $n_i$ = intrinsic carrier concentration ($\approx 1.5 \times 10^{10}$ cm⁻³ for Si at 300K) - $\tau_n$, $\tau_p$ = carrier lifetimes - $C_n$, $C_p$ = Auger coefficients ### 3.4 MOSFET Threshold Voltage The **threshold voltage** determines when Ellsworth's transistors switch on. #### 3.4.1 Threshold Voltage Formula $$ V_T = V_{FB} + 2\phi_F + \frac{\sqrt{2\epsilon_{Si} q N_A (2\phi_F)}}{C_{ox}} $$ **Expanded form:** $$ V_T = \phi_{ms} - \frac{Q_{ox}}{C_{ox}} + 2\phi_F + \frac{\sqrt{2\epsilon_{Si} q N_A (2\phi_F)}}{C_{ox}} $$ #### 3.4.2 Component Definitions **Flatband Voltage:** $$ V_{FB} = \phi_{ms} - \frac{Q_{ox}}{C_{ox}} $$ **Where:** - $\phi_{ms}$ = metal-semiconductor work function difference (V) - $Q_{ox}$ = oxide charge density (C/cm²) **Fermi Potential:** $$ \phi_F = \frac{k_B T}{q} \ln\left(\frac{N_A}{n_i}\right) \quad \text{(p-type)} $$ $$ \phi_F = \frac{k_B T}{q} \ln\left(\frac{N_D}{n_i}\right) \quad \text{(n-type)} $$ **Oxide Capacitance per Unit Area:** $$ C_{ox} = \frac{\epsilon_{ox}}{t_{ox}} $$ **Where:** - $\epsilon_{ox} = 3.9\epsilon_0 = 3.45 \times 10^{-13}$ F/cm - $t_{ox}$ = oxide thickness (cm) #### 3.4.3 Body Effect When substrate (body) is biased relative to source: $$ V_T = V_{T0} + \gamma\left(\sqrt{|2\phi_F + V_{SB}|} - \sqrt{|2\phi_F|}\right) $$ **Body Effect Coefficient:** $$ \gamma = \frac{\sqrt{2\epsilon_{Si} q N_A}}{C_{ox}} = \frac{t_{ox}}{\epsilon_{ox}}\sqrt{2\epsilon_{Si} q N_A} $$ **Typical values:** $\gamma \approx 0.3 - 0.5$ V$^{1/2}$ #### 3.4.4 Threshold Voltage Dependencies **Oxide Thickness Dependence:** $$ \frac{\partial V_T}{\partial t_{ox}} = \frac{\sqrt{2\epsilon_{Si} q N_A (2\phi_F)}}{\epsilon_{ox}} $$ - Thinner oxide → Lower $V_T$ - But: Higher leakage current **Temperature Dependence:** $$ \frac{\partial V_T}{\partial T} \approx -2 \text{ to } -4 \text{ mV/K} $$ **Typical $V_T$ Values:** | Technology | $t_{ox}$ (nm) | $V_T$ (V) | |------------|---------------|-----------| | Ellsworth's DIY | 80-100 | 2-5 | | 1970s Commercial | 50-100 | 1-2 | | Modern (90nm node) | 1.2-2 | 0.3-0.5 | ### 3.5 MOSFET I-V Characteristics The current-voltage relationships for MOSFET operation. #### 3.5.1 Operating Regions ``` - V_DS ──────────────────────► │ │ ┌───────────────────────────── │ │ SATURATION REGION │ │ I_D = const(V_GS) V_GS│ │ │ │ │ ├───────────────────────────── │ │ LINEAR (TRIODE) REGION │ │ I_D ∝ V_DS │ │ ▼ └───────────────────────────── V_DS = V_GS - V_T (Boundary) ``` #### 3.5.2 Linear (Triode) Region **Condition:** $V_{DS} < V_{GS} - V_T$ $$ I_D = \mu_n C_{ox} \frac{W}{L}\left[(V_{GS} - V_T)V_{DS} - \frac{V_{DS}^2}{2}\right] $$ **For small $V_{DS}$:** $$ I_D \approx \mu_n C_{ox} \frac{W}{L}(V_{GS} - V_T)V_{DS} $$ **Channel Resistance:** $$ R_{on} = \frac{V_{DS}}{I_D} = \frac{1}{\mu_n C_{ox} \frac{W}{L}(V_{GS} - V_T)} $$ #### 3.5.3 Saturation Region **Condition:** $V_{DS} \geq V_{GS} - V_T$ $$ I_D = \frac{1}{2}\mu_n C_{ox} \frac{W}{L}(V_{GS} - V_T)^2 $$ **With Channel Length Modulation:** $$ I_D = \frac{1}{2}\mu_n C_{ox} \frac{W}{L}(V_{GS} - V_T)^2(1 + \lambda V_{DS}) $$ **Where:** - $\lambda$ = channel length modulation parameter (V⁻¹) - Typical: $\lambda \approx 0.01 - 0.1$ V⁻¹ #### 3.5.4 Saturation Voltage $$ V_{DS,sat} = V_{GS} - V_T $$ #### 3.5.5 Transconductance **In Saturation:** $$ g_m = \frac{\partial I_D}{\partial V_{GS}} = \mu_n C_{ox} \frac{W}{L}(V_{GS} - V_T) $$ $$ g_m = \sqrt{2\mu_n C_{ox} \frac{W}{L} I_D} $$ #### 3.5.6 Output Conductance $$ g_{ds} = \frac{\partial I_D}{\partial V_{DS}} = \lambda I_D $$ **Output Resistance:** $$ r_o = \frac{1}{g_{ds}} = \frac{1}{\lambda I_D} $$ #### 3.5.7 Subthreshold Region **Condition:** $V_{GS} < V_T$ $$ I_D = I_0 \exp\left(\frac{V_{GS} - V_T}{nV_T}\right)\left(1 - \exp\left(-\frac{V_{DS}}{V_T}\right)\right) $$ **Where:** - $n$ = subthreshold swing factor (typically 1.0 - 1.5) - $I_0$ = characteristic current **Subthreshold Swing:** $$ S = n V_T \ln(10) = 2.3 n V_T \approx 60-100 \text{ mV/decade} $$ ## 4. Practical Applications ### 4.1 Design Calculations for DIY Fabrication #### Example 1: Oxide Growth Time **Given:** - Target oxide thickness: $x = 800$ Å = $8 \times 10^{-6}$ cm - Temperature: $T = 1000°C$ - Wet oxidation **Using Deal-Grove:** At 1000°C wet oxidation: - $B/A = 0.226$ μm/hr = $2.26 \times 10^{-5}$ cm/hr - $B = 0.287$ μm²/hr = $2.87 \times 10^{-10}$ cm²/hr $$ t = \frac{x^2 + Ax}{B} = \frac{x}{B/A} + \frac{x^2}{B} $$ $$ t = \frac{8 \times 10^{-6}}{2.26 \times 10^{-5}} + \frac{(8 \times 10^{-6})^2}{2.87 \times 10^{-10}} $$ $$ t \approx 0.35 + 0.22 = 0.57 \text{ hours} \approx 34 \text{ minutes} $$ #### Example 2: Junction Depth **Given:** - Phosphorus diffusion at 1000°C - Diffusion time: $t = 30$ minutes = 1800 s - $D = 2.5 \times 10^{-14}$ cm²/s **Diffusion Length:** $$ L_D = 2\sqrt{Dt} = 2\sqrt{2.5 \times 10^{-14} \times 1800} $$ $$ L_D = 2\sqrt{4.5 \times 10^{-11}} = 1.34 \times 10^{-5} \text{ cm} = 0.134 \text{ μm} $$ #### Example 3: Threshold Voltage Estimation **Given:** - $t_{ox} = 100$ nm = $10^{-5}$ cm - $N_A = 10^{16}$ cm⁻³ - $\phi_{ms} = -0.9$ V (Al gate on p-Si) **Calculate:** $$ C_{ox} = \frac{3.45 \times 10^{-13}}{10^{-5}} = 3.45 \times 10^{-8} \text{ F/cm}^2 $$ $$ \phi_F = 0.0259 \ln\left(\frac{10^{16}}{1.5 \times 10^{10}}\right) = 0.347 \text{ V} $$ $$ V_T = -0.9 + 2(0.347) + \frac{\sqrt{2 \times 1.04 \times 10^{-12} \times 1.6 \times 10^{-19} \times 10^{16} \times 0.694}}{3.45 \times 10^{-8}} $$ $$ V_T \approx -0.9 + 0.694 + 0.44 = 0.23 \text{ V} $$ ### 4.2 Measurement Verification **I-V Curve Analysis:** 1. Plot $\sqrt{I_D}$ vs. $V_{GS}$ in saturation 2. Linear fit extrapolates to $V_T$ at x-intercept 3. Slope gives $\sqrt{\frac{1}{2}\mu_n C_{ox}\frac{W}{L}}$ **Gate Oxide Quality Check:** $$ E_{breakdown} = \frac{V_{breakdown}}{t_{ox}} > 10 \text{ MV/cm (good quality)} $$ ## 5. Equations ### Key Equations | Process | Governing Equation | |---------|-------------------| | Oxide Growth | $x^2 + Ax = B(t + \tau)$ | | Dopant Diffusion | $\frac{\partial C}{\partial t} = D\frac{\partial^2 C}{\partial x^2}$ | | Charge Transport | $\nabla^2\phi = -\frac{q}{\epsilon}(p - n + N_D^+ - N_A^-)$ | | Threshold Voltage | $V_T = V_{FB} + 2\phi_F + \frac{Q_B}{C_{ox}}$ | | Drain Current (sat) | $I_D = \frac{1}{2}\mu_n C_{ox}\frac{W}{L}(V_{GS} - V_T)^2$ | ### Physical Constants | Constant | Symbol | Value | |----------|--------|-------| | Elementary charge | $q$ | $1.602 \times 10^{-19}$ C | | Boltzmann constant | $k_B$ | $8.617 \times 10^{-5}$ eV/K | | Permittivity of free space | $\epsilon_0$ | $8.854 \times 10^{-14}$ F/cm | | Si permittivity | $\epsilon_{Si}$ | $11.7\epsilon_0$ | | SiO₂ permittivity | $\epsilon_{ox}$ | $3.9\epsilon_0$ | | Intrinsic carrier conc. (Si, 300K) | $n_i$ | $1.5 \times 10^{10}$ cm⁻³ | | Thermal voltage (300K) | $V_T$ | 25.9 mV |
Location with high defect density.
# Semiconductor Chip Manufacturing: Complete Process Guide ## Overview Semiconductor chip manufacturing is one of the most sophisticated and precise manufacturing processes ever developed. This document provides a comprehensive guide following the complete fabrication flow from raw silicon wafer to finished integrated circuit. ## Manufacturing Process Flow (18 Steps) ### FRONT-END-OF-LINE (FEOL) — Transistor Fabrication ``` - ┌─────────────────────────────────────────────────────────────────┐ │ STEP 1: WAFER START & CLEANING │ │ • Incoming QC inspection │ │ • RCA clean (SC-1, SC-2, DHF) │ │ • Surface preparation │ └─────────────────────────────────────────────────────────────────┘ │ ▼ ┌─────────────────────────────────────────────────────────────────┐ │ STEP 2: EPITAXY (EPI) │ │ • Grow single-crystal Si layer │ │ • In-situ doping control │ │ • Strained SiGe for mobility │ └─────────────────────────────────────────────────────────────────┘ │ ▼ ┌─────────────────────────────────────────────────────────────────┐ │ STEP 3: OXIDATION / DIFFUSION │ │ • Thermal gate oxide growth │ │ • STI pad oxide │ │ • High-κ dielectric (HfO₂) │ └─────────────────────────────────────────────────────────────────┘ │ ▼ ┌─────────────────────────────────────────────────────────────────┐ │ STEP 4: CVD (FEOL) │ │ • STI trench fill (HDP-CVD) │ │ • Hard masks (Si₃N₄) │ │ • Spacer deposition │ └─────────────────────────────────────────────────────────────────┘ │ ▼ ┌─────────────────────────────────────────────────────────────────┐ │ STEP 5: PHOTOLITHOGRAPHY │ │ • Coat → Expose (EUV/DUV) → Develop │ │ • Pattern transfer to resist │ │ • Overlay alignment < 2 nm │ └─────────────────────────────────────────────────────────────────┘ │ ▼ ┌─────────────────────────────────────────────────────────────────┐ │ STEP 6: ETCHING │ │ • RIE / Plasma etch │ │ • Resist strip (ashing) │ │ • Post-etch clean │ └─────────────────────────────────────────────────────────────────┘ │ ▼ ┌─────────────────────────────────────────────────────────────────┐ │ STEP 7: ION IMPLANTATION │ │ • Source/Drain doping │ │ • Well implants │ │ • Threshold voltage adjust │ └─────────────────────────────────────────────────────────────────┘ │ ▼ ┌─────────────────────────────────────────────────────────────────┐ │ STEP 8: RAPID THERMAL PROCESSING (RTP) │ │ • Dopant activation │ │ • Damage annealing │ │ • Silicidation (NiSi) │ └─────────────────────────────────────────────────────────────────┘ ``` ### BACK-END-OF-LINE (BEOL) — Interconnect Fabrication ``` - ┌─────────────────────────────────────────────────────────────────┐ │ STEP 9: DEPOSITION (CVD / ALD) │ │ • ILD dielectrics (low-κ) │ │ • Tungsten plugs (W-CVD) │ │ • Etch stop layers │ └─────────────────────────────────────────────────────────────────┘ │ ▼ ┌─────────────────────────────────────────────────────────────────┐ │ STEP 10: DEPOSITION (PVD) │ │ • Barrier layers (TaN/Ta) │ │ • Cu seed layer │ │ • Liner films │ └─────────────────────────────────────────────────────────────────┘ │ ▼ ┌─────────────────────────────────────────────────────────────────┐ │ STEP 11: ELECTROPLATING (ECP) │ │ • Copper bulk fill │ │ • Bottom-up superfill │ │ • Dual damascene process │ └─────────────────────────────────────────────────────────────────┘ │ ▼ ┌─────────────────────────────────────────────────────────────────┐ │ STEP 12: CHEMICAL MECHANICAL POLISHING (CMP) │ │ • Planarization │ │ • Excess metal removal │ │ • Multi-step (Cu → Barrier → Buff) │ └─────────────────────────────────────────────────────────────────┘ ``` ### TESTING & ASSEMBLY — Backend Operations ``` - ┌─────────────────────────────────────────────────────────────────┐ │ STEP 13: WAFER PROBE TEST (EDS) │ │ • Die-level electrical test │ │ • Parametric & functional test │ │ • Bad die inking / mapping │ └─────────────────────────────────────────────────────────────────┘ │ ▼ ┌─────────────────────────────────────────────────────────────────┐ │ STEP 14: BACKGRINDING & DICING │ │ • Wafer thinning │ │ • Blade / Laser / Stealth dicing │ │ • Die singulation │ └─────────────────────────────────────────────────────────────────┘ │ ▼ ┌─────────────────────────────────────────────────────────────────┐ │ STEP 15: DIE ATTACH │ │ • Pick & place │ │ • Epoxy / Eutectic / Solder bond │ │ • Cure cycle │ └─────────────────────────────────────────────────────────────────┘ │ ▼ ┌─────────────────────────────────────────────────────────────────┐ │ STEP 16: WIRE BONDING / FLIP CHIP │ │ • Au/Cu wire bonding │ │ • Flip chip C4 / Cu pillar bumps │ │ • Underfill dispensing │ └─────────────────────────────────────────────────────────────────┘ │ ▼ ┌─────────────────────────────────────────────────────────────────┐ │ STEP 17: ENCAPSULATION │ │ • Transfer molding │ │ • Mold compound injection │ │ • Post-mold cure │ └─────────────────────────────────────────────────────────────────┘ │ ▼ ┌─────────────────────────────────────────────────────────────────┐ │ STEP 18: FINAL TEST → PACKING & SHIP │ │ • Burn-in testing │ │ • Speed binning & class test │ │ • Tape & reel packaging │ └─────────────────────────────────────────────────────────────────┘ ``` # FRONT-END-OF-LINE (FEOL) ## Step 1: Wafer Start & Cleaning ### 1.1 Incoming Quality Control - **Wafer Specifications:** - Diameter: $300 \text{ mm}$ (standard) or $200 \text{ mm}$ (legacy) - Thickness: $775 \pm 20\ \mu\text{m}$ - Resistivity: $1-20\ \Omega\cdot\text{cm}$ - Crystal orientation: $\langle 100 \rangle$ or $\langle 111 \rangle$ - **Inspection Parameters:** - Total Thickness Variation (TTV): $< 5\ \mu\text{m}$ - Surface roughness: $R_a < 0.5 \text{ nm}$ - Particle count: $< 0.1 \text{ particles/cm}^2$ at $\geq 0.1\ \mu\text{m}$ ### 1.2 RCA Cleaning The industry-standard RCA clean removes organic, ionic, and metallic contaminants: **SC-1 (Standard Clean 1) — Organic/Particle Removal:** $$ NH_4OH : H_2O_2 : H_2O = 1:1:5 \quad @ \quad 70-80°C $$ **SC-2 (Standard Clean 2) — Metal Ion Removal:** $$ HCl : H_2O_2 : H_2O = 1:1:6 \quad @ \quad 70-80°C $$ **DHF Dip (Dilute HF) — Native Oxide Removal:** $$ HF : H_2O = 1:50 \quad @ \quad 25°C $$ ### 1.3 Surface Preparation - **Megasonic cleaning**: $0.8-1.5 \text{ MHz}$ frequency - **DI water rinse**: Resistivity $> 18\ \text{M}\Omega\cdot\text{cm}$ - **Spin-rinse-dry (SRD)**: $< 1000 \text{ rpm}$ final spin ## Step 2: Epitaxy (EPI) ### 2.1 Purpose Grows a thin, high-quality single-crystal silicon layer with precisely controlled doping on the substrate. **Why Epitaxy?** - Better crystal quality than bulk wafer - Independent doping control - Reduced latch-up in CMOS - Enables strained silicon (SiGe) ### 2.2 Epitaxial Growth Methods **Chemical Vapor Deposition (CVD) Epitaxy:** $$ SiH_4 \xrightarrow{\Delta} Si + 2H_2 \quad (Silane) $$ $$ SiH_2Cl_2 \xrightarrow{\Delta} Si + 2HCl \quad (Dichlorosilane) $$ $$ SiHCl_3 + H_2 \xrightarrow{\Delta} Si + 3HCl \quad (Trichlorosilane) $$ ### 2.3 Growth Rate The epitaxial growth rate depends on temperature and precursor: $$ R_{growth} = k_0 \cdot P_{precursor} \cdot \exp\left(-\frac{E_a}{k_B T}\right) $$ | Precursor | Temperature | Growth Rate | |-----------|-------------|-------------| | $SiH_4$ | $550-700°C$ | $0.01-0.1\ \mu\text{m/min}$ | | $SiH_2Cl_2$ | $900-1050°C$ | $0.1-1\ \mu\text{m/min}$ | | $SiHCl_3$ | $1050-1150°C$ | $0.5-2\ \mu\text{m/min}$ | | $SiCl_4$ | $1150-1250°C$ | $1-3\ \mu\text{m/min}$ | ### 2.4 In-Situ Doping Dopant gases are introduced during epitaxy: - **N-type**: $PH_3$ (phosphine), $AsH_3$ (arsine) - **P-type**: $B_2H_6$ (diborane) **Doping Concentration:** $$ N_d = \frac{P_{dopant}}{P_{Si}} \cdot \frac{k_{seg}}{1 + k_{seg}} \cdot N_{Si} $$ Where $k_{seg}$ is the segregation coefficient. ### 2.5 Strained Silicon (SiGe) Modern transistors use SiGe for strain engineering: $$ Si_{1-x}Ge_x \quad \text{where} \quad x = 0.2-0.4 $$ **Lattice Mismatch:** $$ \frac{\Delta a}{a} = \frac{a_{SiGe} - a_{Si}}{a_{Si}} \approx 0.042x $$ **Strain-induced mobility enhancement:** - Hole mobility: $+50-100\%$ - Electron mobility: $+20-40\%$ ## Step 3: Oxidation / Diffusion ### 3.1 Thermal Oxidation **Dry Oxidation (Higher Quality, Slower):** $$ Si + O_2 \xrightarrow{900-1200°C} SiO_2 $$ **Wet Oxidation (Lower Quality, Faster):** $$ Si + 2H_2O \xrightarrow{900-1100°C} SiO_2 + 2H_2 $$ ### 3.2 Deal-Grove Model Oxide thickness follows: $$ x_{ox}^2 + A \cdot x_{ox} = B(t + \tau) $$ **Linear Rate Constant:** $$ \frac{B}{A} = \frac{h \cdot C^*}{N_1} $$ **Parabolic Rate Constant:** $$ B = \frac{2D_{eff} \cdot C^*}{N_1} $$ Where: - $C^*$ = equilibrium oxidant concentration - $N_1$ = number of oxidant molecules per unit volume of oxide - $D_{eff}$ = effective diffusion coefficient - $h$ = surface reaction rate constant ### 3.3 Oxide Types in CMOS | Oxide Type | Thickness | Purpose | |------------|-----------|---------| | Gate Oxide | $1-5 \text{ nm}$ | Transistor gate dielectric | | STI Pad Oxide | $10-20 \text{ nm}$ | Stress buffer for STI | | Tunnel Oxide | $8-10 \text{ nm}$ | Flash memory | | Sacrificial Oxide | $10-50 \text{ nm}$ | Surface damage removal | ### 3.4 High-κ Dielectrics Modern nodes use high-κ materials instead of $SiO_2$: **Equivalent Oxide Thickness (EOT):** $$ EOT = t_{high-\kappa} \cdot \frac{\kappa_{SiO_2}}{\kappa_{high-\kappa}} = t_{high-\kappa} \cdot \frac{3.9}{\kappa_{high-\kappa}} $$ | Material | Dielectric Constant ($\kappa$) | Bandgap (eV) | |----------|-------------------------------|--------------| | $SiO_2$ | $3.9$ | $9.0$ | | $Si_3N_4$ | $7.5$ | $5.3$ | | $Al_2O_3$ | $9$ | $8.8$ | | $HfO_2$ | $20-25$ | $5.8$ | | $ZrO_2$ | $25$ | $5.8$ | ## Step 4: CVD (FEOL) — Dielectrics, Hard Masks, Spacers ### 4.1 Purpose in FEOL CVD in FEOL is critical for depositing: - **STI (Shallow Trench Isolation)** fill oxide - **Gate hard masks** ($Si_3N_4$, $SiO_2$) - **Spacer materials** ($Si_3N_4$, $SiCO$) - **Pre-metal dielectric (ILD₀)** - **Etch stop layers** ### 4.2 CVD Methods **LPCVD (Low Pressure CVD):** - Pressure: $0.1-10 \text{ Torr}$ - Temperature: $400-900°C$ - Excellent uniformity - Batch processing **PECVD (Plasma Enhanced CVD):** - Pressure: $0.1-10 \text{ Torr}$ - Temperature: $200-400°C$ - Lower thermal budget - Single wafer processing **HDPCVD (High Density Plasma CVD):** - Simultaneous deposition and sputtering - Superior gap fill for STI - Pressure: $1-10 \text{ mTorr}$ **SACVD (Sub-Atmospheric CVD):** - Pressure: $200-600 \text{ Torr}$ - Good conformality - Used for BPSG, USG ### 4.3 Key FEOL CVD Films **Silicon Nitride ($Si_3N_4$):** $$ 3SiH_4 + 4NH_3 \xrightarrow{LPCVD, 750°C} Si_3N_4 + 12H_2 $$ $$ 3SiH_2Cl_2 + 4NH_3 \xrightarrow{LPCVD, 750°C} Si_3N_4 + 6HCl + 6H_2 $$ **TEOS Oxide ($SiO_2$):** $$ Si(OC_2H_5)_4 \xrightarrow{PECVD, 400°C} SiO_2 + \text{byproducts} $$ **HDP Oxide (STI Fill):** $$ SiH_4 + O_2 \xrightarrow{HDP-CVD} SiO_2 + 2H_2 $$ ### 4.4 CVD Process Parameters | Parameter | LPCVD | PECVD | HDPCVD | |-----------|-------|-------|--------| | Pressure | $0.1-10$ Torr | $0.1-10$ Torr | $1-10$ mTorr | | Temperature | $400-900°C$ | $200-400°C$ | $300-450°C$ | | Uniformity | $< 2\%$ | $< 3\%$ | $< 3\%$ | | Step Coverage | Conformal | $50-80\%$ | Gap fill | | Throughput | High (batch) | Medium | Medium | ### 4.5 Film Properties | Film | Stress | Density | Application | |------|--------|---------|-------------| | LPCVD $Si_3N_4$ | $1.0-1.2$ GPa (tensile) | $3.1 \text{ g/cm}^3$ | Hard mask, spacer | | PECVD $Si_3N_4$ | $-200$ to $+200$ MPa | $2.5-2.8 \text{ g/cm}^3$ | Passivation | | LPCVD $SiO_2$ | $-300$ MPa (compressive) | $2.2 \text{ g/cm}^3$ | Spacer | | HDP $SiO_2$ | $-100$ to $-300$ MPa | $2.2 \text{ g/cm}^3$ | STI fill | ## Step 5: Photolithography ### 5.1 Process Sequence ``` HMDS Prime → Spin Coat → Soft Bake → Align → Expose → PEB → Develop → Hard Bake ``` ### 5.2 Resolution Limits **Rayleigh Criterion:** $$ CD_{min} = k_1 \cdot \frac{\lambda}{NA} $$ **Depth of Focus:** $$ DOF = k_2 \cdot \frac{\lambda}{NA^2} $$ Where: - $CD_{min}$ = minimum critical dimension - $k_1$ = process factor ($0.25-0.4$ for advanced nodes) - $k_2$ = depth of focus factor ($\approx 0.5$) - $\lambda$ = wavelength - $NA$ = numerical aperture ### 5.3 Exposure Systems Evolution | Generation | $\lambda$ (nm) | $NA$ | $k_1$ | Resolution | |------------|----------------|------|-------|------------| | G-line | $436$ | $0.4$ | $0.8$ | $870 \text{ nm}$ | | I-line | $365$ | $0.6$ | $0.7$ | $425 \text{ nm}$ | | KrF | $248$ | $0.8$ | $0.5$ | $155 \text{ nm}$ | | ArF Dry | $193$ | $0.85$ | $0.4$ | $90 \text{ nm}$ | | ArF Immersion | $193$ | $1.35$ | $0.35$ | $50 \text{ nm}$ | | EUV | $13.5$ | $0.33$ | $0.35$ | $14 \text{ nm}$ | | High-NA EUV | $13.5$ | $0.55$ | $0.30$ | $8 \text{ nm}$ | ### 5.4 Immersion Lithography Uses water ($n = 1.44$) between lens and wafer: $$ NA_{immersion} = n_{fluid} \cdot \sin\theta_{max} $$ **Maximum NA achievable:** - Dry: $NA \approx 0.93$ - Water immersion: $NA \approx 1.35$ ### 5.5 EUV Lithography **Light Source:** - Tin ($Sn$) plasma at $\lambda = 13.5 \text{ nm}$ - CO₂ laser ($10.6\ \mu\text{m}$) hits Sn droplets - Conversion efficiency: $\eta \approx 5\%$ **Power Requirements:** $$ P_{source} = \frac{P_{wafer}}{\eta_{optics} \cdot \eta_{conversion}} \approx \frac{250W}{0.04 \cdot 0.05} = 125 \text{ kW} $$ **Multilayer Mirror Reflectivity:** - Mo/Si bilayer: $\sim 70\%$ per reflection - 6 mirrors: $(0.70)^6 \approx 12\%$ total throughput ### 5.6 Photoresist Chemistry **Chemically Amplified Resist (CAR):** $$ \text{PAG} \xrightarrow{h\nu} H^+ \quad \text{(Photoacid Generator)} $$ $$ \text{Protected Polymer} + H^+ \xrightarrow{PEB} \text{Deprotected Polymer} + H^+ $$ **Acid Diffusion Length:** $$ L_D = \sqrt{D \cdot t_{PEB}} \approx 10-50 \text{ nm} $$ ### 5.7 Overlay Control **Overlay Budget:** $$ \sigma_{overlay} = \sqrt{\sigma_{tool}^2 + \sigma_{process}^2 + \sigma_{wafer}^2} $$ Modern requirement: $< 2 \text{ nm}$ (3σ) ## Step 6: Etching ### 6.1 Etch Methods Comparison | Property | Wet Etch | Dry Etch (RIE) | |----------|----------|----------------| | Profile | Isotropic | Anisotropic | | Selectivity | High ($>100:1$) | Moderate ($10-50:1$) | | Damage | None | Ion damage possible | | Resolution | $> 1\ \mu\text{m}$ | $< 10 \text{ nm}$ | | Throughput | High | Lower | ### 6.2 Dry Etch Mechanisms **Physical Sputtering:** $$ Y_{sputter} = \frac{\text{Atoms removed}}{\text{Incident ion}} $$ **Chemical Etching:** $$ \text{Material} + \text{Reactive Species} \rightarrow \text{Volatile Products} $$ **Reactive Ion Etching (RIE):** Combines both mechanisms for anisotropic profiles. ### 6.3 Plasma Chemistry **Silicon Etching:** $$ Si + 4F^* \rightarrow SiF_4 \uparrow $$ $$ Si + 2Cl^* \rightarrow SiCl_2 \uparrow $$ **Oxide Etching:** $$ SiO_2 + 4F^* + C^* \rightarrow SiF_4 \uparrow + CO_2 \uparrow $$ **Nitride Etching:** $$ Si_3N_4 + 12F^* \rightarrow 3SiF_4 \uparrow + 2N_2 \uparrow $$ ### 6.4 Etch Parameters **Etch Rate:** $$ ER = \frac{\Delta h}{\Delta t} \quad [\text{nm/min}] $$ **Selectivity:** $$ S = \frac{ER_{target}}{ER_{mask}} $$ **Anisotropy:** $$ A = 1 - \frac{ER_{lateral}}{ER_{vertical}} $$ $A = 1$ is perfectly anisotropic (vertical sidewalls) **Aspect Ratio:** $$ AR = \frac{\text{Depth}}{\text{Width}} $$ Modern HAR (High Aspect Ratio) etching: $AR > 100:1$ ### 6.5 Etch Gas Chemistry | Material | Primary Etch Gas | Additives | Products | |----------|------------------|-----------|----------| | Si | $SF_6$, $Cl_2$, $HBr$ | $O_2$ | $SiF_4$, $SiCl_4$, $SiBr_4$ | | $SiO_2$ | $CF_4$, $C_4F_8$ | $CHF_3$, $O_2$ | $SiF_4$, $CO$, $CO_2$ | | $Si_3N_4$ | $CF_4$, $CHF_3$ | $O_2$ | $SiF_4$, $N_2$, $CO$ | | Poly-Si | $Cl_2$, $HBr$ | $O_2$ | $SiCl_4$, $SiBr_4$ | | W | $SF_6$ | $N_2$ | $WF_6$ | | Cu | Not practical | Use CMP | — | ### 6.6 Post-Etch Processing **Resist Strip (Ashing):** $$ \text{Photoresist} + O^* \xrightarrow{plasma} CO_2 + H_2O $$ **Wet Clean (Post-Etch Residue Removal):** - Dilute HF for polymer residue - SC-1 for particles - Proprietary etch residue removers ## Step 7: Ion Implantation ### 7.1 Purpose Introduces dopant atoms into silicon with precise control of: - Dose (atoms/cm²) - Energy (depth) - Species (n-type or p-type) ### 7.2 Implanter Components ``` Ion Source → Mass Analyzer → Acceleration → Beam Scanning → Target Wafer ``` ### 7.3 Dopant Selection **N-type (Donors):** | Dopant | Mass (amu) | $E_d$ (meV) | Application | |--------|------------|-------------|-------------| | $P$ | $31$ | $45$ | NMOS S/D, wells | | $As$ | $75$ | $54$ | NMOS S/D (shallow) | | $Sb$ | $122$ | $39$ | Buried layers | **P-type (Acceptors):** | Dopant | Mass (amu) | $E_a$ (meV) | Application | |--------|------------|-------------|-------------| | $B$ | $11$ | $45$ | PMOS S/D, wells | | $BF_2$ | $49$ | — | Ultra-shallow junctions | | $In$ | $115$ | $160$ | Halo implants | ### 7.4 Implantation Physics **Ion Energy:** $$ E = qV_{acc} $$ Typical range: $0.2 \text{ keV} - 3 \text{ MeV}$ **Dose:** $$ \Phi = \frac{I_{beam} \cdot t}{q \cdot A} $$ Where: - $\Phi$ = dose (ions/cm²), typical: $10^{11} - 10^{16}$ - $I_{beam}$ = beam current - $t$ = implant time - $A$ = implanted area **Beam Current Requirements:** - High dose (S/D): $1-20 \text{ mA}$ - Medium dose (wells): $100\ \mu\text{A} - 1 \text{ mA}$ - Low dose (threshold adjust): $1-100\ \mu\text{A}$ ### 7.5 Depth Distribution **Gaussian Profile (First Order):** $$ N(x) = \frac{\Phi}{\sqrt{2\pi} \cdot \Delta R_p} \cdot \exp\left[-\frac{(x - R_p)^2}{2(\Delta R_p)^2}\right] $$ Where: - $R_p$ = projected range (mean depth) - $\Delta R_p$ = straggle (standard deviation) **Peak Concentration:** $$ N_{peak} = \frac{\Phi}{\sqrt{2\pi} \cdot \Delta R_p} \approx \frac{0.4 \cdot \Phi}{\Delta R_p} $$ ### 7.6 Range Tables (in Silicon) | Ion | Energy (keV) | $R_p$ (nm) | $\Delta R_p$ (nm) | |-----|--------------|------------|-------------------| | $B$ | $10$ | $35$ | $15$ | | $B$ | $50$ | $160$ | $55$ | | $P$ | $30$ | $40$ | $15$ | | $P$ | $100$ | $120$ | $45$ | | $As$ | $50$ | $35$ | $12$ | | $As$ | $150$ | $95$ | $35$ | ### 7.7 Channeling When ions align with crystal axes, they penetrate deeper (channeling). **Prevention Methods:** - Tilt wafer $7°$ off-axis - Rotate wafer during implant - Pre-amorphization implant (PAI) - Screen oxide ### 7.8 Implant Damage **Damage Density:** $$ N_{damage} \propto \Phi \cdot \frac{dE}{dx}_{nuclear} $$ **Amorphization Threshold:** - Si becomes amorphous above critical dose - For As at RT: $\Phi_{crit} \approx 10^{14} \text{ cm}^{-2}$ ## Step 8: Rapid Thermal Processing (RTP) ### 8.1 Purpose - **Dopant Activation**: Move implanted atoms to substitutional sites - **Damage Annealing**: Repair crystal damage from implantation - **Silicidation**: Form metal silicides for contacts ### 8.2 RTP Methods | Method | Temperature | Time | Application | |--------|-------------|------|-------------| | Furnace Anneal | $800-1100°C$ | $30-60$ min | Diffusion, oxidation | | Spike RTA | $1000-1100°C$ | $1-5$ s | Dopant activation | | Flash Anneal | $1100-1350°C$ | $1-10$ ms | USJ activation | | Laser Anneal | $>1300°C$ | $100$ ns - $1\ \mu$s | Surface activation | ### 8.3 Dopant Activation **Electrical Activation:** $$ n_{active} = N_d \cdot \left(1 - \exp\left(-\frac{t}{\tau}\right)\right) $$ Where $\tau$ = activation time constant **Solid Solubility Limit:** Maximum electrically active concentration at given temperature. | Dopant | Solubility at $1000°C$ (cm⁻³) | |--------|-------------------------------| | $B$ | $2 \times 10^{20}$ | | $P$ | $1.2 \times 10^{21}$ | | $As$ | $1.5 \times 10^{21}$ | ### 8.4 Diffusion During Annealing **Fick's Second Law:** $$ \frac{\partial C}{\partial t} = D \cdot \frac{\partial^2 C}{\partial x^2} $$ **Diffusion Coefficient:** $$ D = D_0 \cdot \exp\left(-\frac{E_a}{k_B T}\right) $$ **Diffusion Length:** $$ L_D = 2\sqrt{D \cdot t} $$ ### 8.5 Transient Enhanced Diffusion (TED) Implant damage creates excess interstitials that enhance diffusion: $$ D_{TED} = D_{intrinsic} \cdot \left(1 + \frac{C_I}{C_I^*}\right) $$ Where: - $C_I$ = interstitial concentration - $C_I^*$ = equilibrium interstitial concentration **TED Mitigation:** - Low-temperature annealing first - Carbon co-implantation - Millisecond annealing ### 8.6 Silicidation **Self-Aligned Silicide (Salicide) Process:** $$ M + Si \xrightarrow{\Delta} M_xSi_y $$ | Silicide | Formation Temp | Resistivity ($\mu\Omega\cdot\text{cm}$) | Consumption Ratio | |----------|----------------|---------------------|-------------------| | $TiSi_2$ | $700-850°C$ | $13-20$ | 2.27 nm Si/nm Ti | | $CoSi_2$ | $600-800°C$ | $15-20$ | 3.64 nm Si/nm Co | | $NiSi$ | $400-600°C$ | $15-20$ | 1.83 nm Si/nm Ni | **Modern Choice: NiSi** - Lower formation temperature - Less silicon consumption - Compatible with SiGe # BACK-END-OF-LINE (BEOL) ## Step 9: Deposition (CVD / ALD) — ILD, Tungsten Plugs ### 9.1 Inter-Layer Dielectric (ILD) **Purpose:** - Electrical isolation between metal layers - Planarization base - Capacitance control **ILD Materials Evolution:** | Generation | Material | $\kappa$ | Application | |------------|----------|----------|-------------| | Al era | $SiO_2$ | $4.0$ | 0.25 $\mu$m+ | | Early Cu | FSG ($SiO_xF_y$) | $3.5$ | 180-130 nm | | Low-κ | SiCOH | $2.7-3.0$ | 90-45 nm | | ULK | Porous SiCOH | $2.2-2.5$ | 32 nm+ | | Air gap | Air/$SiO_2$ | $< 2.0$ | 14 nm+ | ### 9.2 CVD Oxide Processes **PECVD TEOS:** $$ Si(OC_2H_5)_4 + O_2 \xrightarrow{plasma} SiO_2 + \text{byproducts} $$ **SACVD TEOS/Ozone:** $$ Si(OC_2H_5)_4 + O_3 \xrightarrow{400°C} SiO_2 + \text{byproducts} $$ ### 9.3 ALD (Atomic Layer Deposition) **Characteristics:** - Self-limiting surface reactions - Atomic-level thickness control - Excellent conformality (100%) - Essential for advanced nodes **Growth Per Cycle (GPC):** $$ GPC \approx 0.5-2 \text{ Å/cycle} $$ **ALD $Al_2O_3$ Example:** ``` Cycle: 1. TMA pulse: Al(CH₃)₃ + surface-OH → surface-O-Al(CH₃)₂ + CH₄ 2. Purge 3. H₂O pulse: surface-O-Al(CH₃)₂ + H₂O → surface-O-Al-OH + CH₄ 4. Purge → Repeat ``` **ALD $HfO_2$ (High-κ Gate):** - Precursor: $Hf(N(CH_3)_2)_4$ (TDMAH) or $HfCl_4$ - Oxidant: $H_2O$ or $O_3$ - Temperature: $250-350°C$ - GPC: $\sim 1 \text{ Å/cycle}$ ### 9.4 Tungsten CVD (Contact Plugs) **Nucleation Layer:** $$ WF_6 + SiH_4 \rightarrow W + SiF_4 + 3H_2 $$ **Bulk Fill:** $$ WF_6 + 3H_2 \xrightarrow{300-450°C} W + 6HF $$ **Process Parameters:** - Temperature: $400-450°C$ - Pressure: $30-90 \text{ Torr}$ - Deposition rate: $100-400 \text{ nm/min}$ - Resistivity: $8-15\ \mu\Omega\cdot\text{cm}$ ### 9.5 Etch Stop Layers **Silicon Carbide ($SiC$) / Nitrogen-doped $SiC$:** $$ \text{Precursor: } (CH_3)_3SiH \text{ (Trimethylsilane)} $$ - $\kappa \approx 4-5$ - Provides etch selectivity to oxide - Acts as Cu diffusion barrier ## Step 10: Deposition (PVD) — Barriers, Seed Layers ### 10.1 PVD Sputtering Fundamentals **Sputter Yield:** $$ Y = \frac{\text{Target atoms ejected}}{\text{Incident ion}} $$ | Target | Yield (Ar⁺ at 500 eV) | |--------|----------------------| | Al | 1.2 | | Cu | 2.3 | | Ti | 0.6 | | Ta | 0.6 | | W | 0.6 | ### 10.2 Barrier Layers **Purpose:** - Prevent Cu diffusion into dielectric - Promote adhesion - Provide nucleation for seed layer **TaN/Ta Bilayer (Standard):** - TaN: Cu diffusion barrier, $\rho \approx 200\ \mu\Omega\cdot\text{cm}$ - Ta: Adhesion/nucleation, $\rho \approx 15\ \mu\Omega\cdot\text{cm}$ - Total thickness: $3-10 \text{ nm}$ **Advanced Barriers:** - TiN: Compatible with W plugs - Ru: Enables direct Cu plating - Co: Next-generation contacts ### 10.3 PVD Methods **DC Magnetron Sputtering:** - For conductive targets (Ta, Ti, Cu) - High deposition rates **RF Magnetron Sputtering:** - For insulating targets - Lower rates **Ionized PVD (iPVD):** - High ion fraction for improved step coverage - Essential for high aspect ratio features **Collimated PVD:** - Physical collimator for directionality - Reduced deposition rate ### 10.4 Copper Seed Layer **Requirements:** - Continuous coverage (no voids) - Thickness: $20-80 \text{ nm}$ - Good adhesion to barrier - Uniform grain structure **Deposition:** $$ \text{Ar}^+ + \text{Cu}_{\text{target}} \rightarrow \text{Cu}_{\text{atoms}} \rightarrow \text{Cu}_{\text{film}} $$ **Step Coverage Challenge:** $$ \text{Step Coverage} = \frac{t_{sidewall}}{t_{field}} \times 100\% $$ For trenches with $AR > 3$, iPVD is required. ## Step 11: Electroplating (ECP) — Copper Fill ### 11.1 Electrochemical Fundamentals **Copper Reduction:** $$ Cu^{2+} + 2e^- \rightarrow Cu $$ **Faraday's Law:** $$ m = \frac{I \cdot t \cdot M}{n \cdot F} $$ Where: - $m$ = mass deposited - $I$ = current - $t$ = time - $M$ = molar mass ($63.5 \text{ g/mol}$ for Cu) - $n$ = electrons transferred ($2$ for Cu) - $F$ = Faraday constant ($96,485 \text{ C/mol}$) **Deposition Rate:** $$ R = \frac{I \cdot M}{n \cdot F \cdot \rho \cdot A} $$ ### 11.2 Superfilling (Bottom-Up Fill) **Additives Enable Void-Free Fill:** | Additive Type | Function | Example | |---------------|----------|---------| | Accelerator | Promotes deposition at bottom | SPS (bis-3-sulfopropyl disulfide) | | Suppressor | Inhibits deposition at top | PEG (polyethylene glycol) | | Leveler | Controls shape | JGB (Janus Green B) | **Superfilling Mechanism:** 1. Suppressor adsorbs on all surfaces 2. Accelerator concentrates at feature bottom 3. As feature fills, accelerator becomes more concentrated 4. Bottom-up fill achieved ### 11.3 ECP Process Parameters | Parameter | Value | |-----------|-------| | Electrolyte | $CuSO_4$ (0.25-1.0 M) + $H_2SO_4$ | | Temperature | $20-25°C$ | | Current Density | $5-60 \text{ mA/cm}^2$ | | Deposition Rate | $100-600 \text{ nm/min}$ | | Bath pH | $< 1$ | ### 11.4 Damascene Process **Single Damascene:** 1. Deposit ILD 2. Pattern and etch trenches 3. Deposit barrier (PVD TaN/Ta) 4. Deposit seed (PVD Cu) 5. Electroplate Cu 6. CMP to planarize **Dual Damascene:** 1. Deposit ILD stack 2. Pattern and etch vias 3. Pattern and etch trenches 4. Single barrier + seed + plate step 5. CMP - More efficient (fewer steps) - Via-first or trench-first approaches ### 11.5 Overburden Requirements $$ t_{overburden} = t_{trench} + t_{margin} $$ Typical: $300-1000 \text{ nm}$ over field ## Step 12: Chemical Mechanical Polishing (CMP) ### 12.1 Preston Equation $$ MRR = K_p \cdot P \cdot V $$ Where: - $MRR$ = Material Removal Rate (nm/min) - $K_p$ = Preston coefficient - $P$ = down pressure - $V$ = relative velocity ### 12.2 CMP Components **Slurry Composition:** | Component | Function | Example | |-----------|----------|---------| | Abrasive | Mechanical removal | $SiO_2$, $Al_2O_3$, $CeO_2$ | | Oxidizer | Chemical modification | $H_2O_2$, $KIO_3$ | | Complexing agent | Metal dissolution | Glycine, citric acid | | Surfactant | Particle dispersion | Various | | Corrosion inhibitor | Protect Cu | BTA (benzotriazole) | **Abrasive Particle Size:** $$ d_{particle} = 20-200 \text{ nm} $$ ### 12.3 CMP Process Parameters | Parameter | Cu CMP | Oxide CMP | W CMP | |-----------|--------|-----------|-------| | Pressure | $1-3 \text{ psi}$ | $3-7 \text{ psi}$ | $3-5 \text{ psi}$ | | Platen speed | $50-100 \text{ rpm}$ | $50-100 \text{ rpm}$ | $50-100 \text{ rpm}$ | | Slurry flow | $150-300 \text{ mL/min}$ | $150-300 \text{ mL/min}$ | $150-300 \text{ mL/min}$ | | Removal rate | $300-800 \text{ nm/min}$ | $100-300 \text{ nm/min}$ | $200-400 \text{ nm/min}$ | ### 12.4 Planarization Metrics **Within-Wafer Non-Uniformity (WIWNU):** $$ WIWNU = \frac{\sigma}{mean} \times 100\% $$ Target: $< 3\%$ **Dishing (Cu):** $$ D_{dish} = t_{field} - t_{trench} $$ Occurs because Cu polishes faster than barrier. **Erosion (Dielectric):** $$ E_{erosion} = t_{oxide,initial} - t_{oxide,final} $$ Occurs in dense pattern areas. ### 12.5 Multi-Step Cu CMP **Step 1 (Bulk Cu removal):** - High rate slurry - Remove overburden - Stop on barrier **Step 2 (Barrier removal):** - Different chemistry - Remove TaN/Ta - Stop on oxide **Step 3 (Buff/clean):** - Low pressure - Remove residues - Final surface preparation # TESTING & ASSEMBLY ## Step 13: Wafer Probe Test (EDS) ### 13.1 Purpose - Test every die on wafer before dicing - Identify defective dies (ink marking) - Characterize process performance - Bin dies by speed grade ### 13.2 Test Types **Parametric Testing:** - Threshold voltage: $V_{th}$ - Drive current: $I_{on}$ - Leakage current: $I_{off}$ - Contact resistance: $R_c$ - Sheet resistance: $R_s$ **Functional Testing:** - Memory BIST (Built-In Self-Test) - Logic pattern testing - At-speed testing ### 13.3 Key Device Equations **MOSFET On-Current (Saturation):** $$ I_{DS,sat} = \frac{W}{L} \cdot \mu \cdot C_{ox} \cdot \frac{(V_{GS} - V_{th})^2}{2} \cdot (1 + \lambda V_{DS}) $$ **Subthreshold Current:** $$ I_{sub} = I_0 \cdot \exp\left(\frac{V_{GS} - V_{th}}{n \cdot V_T}\right) \cdot \left(1 - \exp\left(\frac{-V_{DS}}{V_T}\right)\right) $$ **Subthreshold Swing:** $$ SS = n \cdot \frac{k_B T}{q} \cdot \ln(10) \approx 60 \text{ mV/dec} \times n \quad @ \quad 300K $$ Ideal: $SS = 60 \text{ mV/dec}$ ($n = 1$) **On/Off Ratio:** $$ \frac{I_{on}}{I_{off}} > 10^6 $$ ### 13.4 Yield Models **Poisson Model:** $$ Y = e^{-D_0 \cdot A} $$ **Murphy's Model:** $$ Y = \left(\frac{1 - e^{-D_0 A}}{D_0 A}\right)^2 $$ **Negative Binomial Model:** $$ Y = \left(1 + \frac{D_0 A}{\alpha}\right)^{-\alpha} $$ Where: - $Y$ = yield - $D_0$ = defect density (defects/cm²) - $A$ = die area - $\alpha$ = clustering parameter ### 13.5 Speed Binning Dies sorted into performance grades: - Bin 1: Highest speed (premium) - Bin 2: Standard speed - Bin 3: Lower speed (budget) - Fail: Defective ## Step 14: Backgrinding & Dicing ### 14.1 Wafer Thinning (Backgrinding) **Purpose:** - Reduce package height - Improve thermal dissipation - Enable TSV reveal - Required for stacking **Final Thickness:** | Application | Thickness | |-------------|-----------| | Standard | $200-300\ \mu\text{m}$ | | Thin packages | $50-100\ \mu\text{m}$ | | 3D stacking | $20-50\ \mu\text{m}$ | **Process:** 1. Mount wafer face-down on tape/carrier 2. Coarse grind (diamond wheel) 3. Fine grind 4. Stress relief (CMP or dry polish) 5. Optional: Backside metallization ### 14.2 Dicing Methods **Blade Dicing:** - Diamond-coated blade - Kerf width: $20-50\ \mu\text{m}$ - Speed: $10-100 \text{ mm/s}$ - Standard method **Laser Dicing:** - Ablation or stealth dicing - Kerf width: $< 10 \text{ μm}$ - Higher throughput - Less chipping **Stealth Dicing (SD):** - Laser creates internal modification - Expansion tape breaks wafer - Zero kerf loss - Best for thin wafers **Plasma Dicing:** - Deep RIE through streets - Irregular die shapes possible - No mechanical stress ### 14.3 Dies Per Wafer **Gross Die Per Wafer:** $$ GDW = \frac{\pi D^2}{4 \cdot A_{die}} - \frac{\pi D}{\sqrt{2 \cdot A_{die}}} $$ Where: - $D$ = wafer diameter - $A_{die}$ = die area (including scribe) **Example (300mm wafer, 100mm² die):** $$ GDW = \frac{\pi \times 300^2}{4 \times 100} - \frac{\pi \times 300}{\sqrt{200}} \approx 640 \text{ dies} $$ ## Step 15: Die Attach ### 15.1 Methods | Method | Material | Temperature | Application | |--------|----------|-------------|-------------| | Epoxy | Ag-filled epoxy | $150-175°C$ | Standard | | Eutectic | Au-Si | $363°C$ | High reliability | | Solder | SAC305 | $217-227°C$ | Power devices | | Sintering | Ag paste | $250-300°C$ | High power | ### 15.2 Thermal Performance **Thermal Resistance:** $$ R_{th} = \frac{t}{k \cdot A} $$ Where: - $t$ = bond line thickness (BLT) - $k$ = thermal conductivity - $A$ = die area | Material | $k$ (W/m$\cdot$K) | |----------|-------------| | Ag-filled epoxy | $2-25$ | | SAC solder | $60$ | | Au-Si eutectic | $27$ | | Sintered Ag | $200-250$ | ### 15.3 Die Attach Requirements - **BLT uniformity**: $\pm 5 \text{ μm}$ - **Void content**: $< 5\%$ (power devices) - **Die tilt**: $< 1°$ - **Placement accuracy**: $\pm 25 \text{ μm}$ ## Step 16: Wire Bonding / Flip Chip ### 16.1 Wire Bonding **Wire Materials:** | Material | Diameter | Resistivity | Application | |----------|----------|-------------|-------------| | Au | $15-50\ \mu\text{m}$ | $2.2\ \mu\Omega\cdot\text{cm}$ | Premium, RF | | Cu | $15-50\ \mu\text{m}$ | $1.7\ \mu\Omega\cdot\text{cm}$ | Cost-effective | | Ag | $15-25\ \mu\text{m}$ | $1.6\ \mu\Omega\cdot\text{cm}$ | LED, power | | Al | $25-500\ \mu\text{m}$ | $2.7\ \mu\Omega\cdot\text{cm}$ | Power, ribbon | **Thermosonic Ball Bonding:** - Temperature: $150-220°C$ - Ultrasonic frequency: $60-140 \text{ kHz}$ - Bond force: $15-100 \text{ gf}$ - Bond time: $5-20 \text{ ms}$ **Wire Resistance:** $$ R_{wire} = \rho \cdot \frac{L}{\pi r^2} $$ ### 16.2 Flip Chip **Advantages over Wire Bonding:** - Higher I/O density - Lower inductance - Better thermal path - Higher frequency capability **Bump Types:** | Type | Pitch | Material | Application | |------|-------|----------|-------------| | C4 (Controlled Collapse Chip Connection) | $150-250 \text{ μm}$ | Pb-Sn, SAC | Standard | | Cu pillar | $40-100 \text{ μm}$ | Cu + solder cap | Fine pitch | | Micro-bump | $10-40 \text{ μm}$ | Cu + SnAg | 2.5D/3D | **Bump Height:** $$ h_{bump} \approx 50-100 \text{ μm} \quad \text{(C4)} $$ $$ h_{pillar} \approx 30-50 \text{ μm} \quad \text{(Cu pillar)} $$ ### 16.3 Underfill **Purpose:** - Distribute thermal stress - Protect bumps - Improve reliability **CTE Matching:** $$ \alpha_{underfill} \approx 25-30 \text{ ppm/°C} $$ (Between Si at $3 \text{ ppm/°C}$ and substrate at $17 \text{ ppm/°C}$) ## Step 17: Encapsulation ### 17.1 Mold Compound Properties | Property | Value | Unit | |----------|-------|------| | Filler content | $70-90$ | wt% ($SiO_2$) | | CTE ($\alpha_1$, below $T_g$) | $8-15$ | ppm/°C | | CTE ($\alpha_2$, above $T_g$) | $30-50$ | ppm/°C | | Glass transition ($T_g$) | $150-175$ | °C | | Thermal conductivity | $0.7-3$ | W/m$\cdot$K | | Flexural modulus | $15-25$ | GPa | | Moisture absorption | $< 0.3$ | wt% | ### 17.2 Transfer Molding Process **Parameters:** - Mold temperature: $175-185°C$ - Transfer pressure: $5-10 \text{ MPa}$ - Transfer time: $10-20 \text{ s}$ - Cure time: $60-120 \text{ s}$ - Post-mold cure: $4-8 \text{ hrs}$ at $175°C$ **Cure Kinetics (Kamal Model):** $$ \frac{d\alpha}{dt} = (k_1 + k_2 \alpha^m)(1-\alpha)^n $$ Where: - $\alpha$ = degree of cure (0 to 1) - $k_1, k_2$ = rate constants - $m, n$ = reaction orders ### 17.3 Package Types **Traditional:** - DIP (Dual In-line Package) - QFP (Quad Flat Package) - QFN (Quad Flat No-lead) - BGA (Ball Grid Array) **Advanced:** - WLCSP (Wafer Level Chip Scale Package) - FCBGA (Flip Chip BGA) - SiP (System in Package) - 2.5D/3D IC ## Step 18: Final Test → Packing & Ship ### 18.1 Final Test **Test Levels:** - **Hot Test**: $85-125°C$ - **Cold Test**: $-40$ to $0°C$ - **Room Temp Test**: $25°C$ **Burn-In:** - Temperature: $125-150°C$ - Voltage: $V_{DD} + 10\%$ - Duration: $24-168 \text{ hrs}$ - Accelerates infant mortality failures **Acceleration Factor (Arrhenius):** $$ AF = \exp\left[\frac{E_a}{k_B}\left(\frac{1}{T_{use}} - \frac{1}{T_{stress}}\right)\right] $$ Where $E_a \approx 0.7 \text{ eV}$ (typical) ### 18.2 Quality Metrics **DPPM (Defective Parts Per Million):** $$ DPPM = \frac{\text{Failures}}{\text{Units Shipped}} \times 10^6 $$ | Market | DPPM Target | |--------|-------------| | Consumer | $< 500$ | | Industrial | $< 100$ | | Automotive | $< 10$ | | Medical | $< 1$ | ### 18.3 Reliability Testing **Electromigration (Black's Equation):** $$ MTTF = A \cdot J^{-n} \cdot \exp\left(\frac{E_a}{k_B T}\right) $$ Where: - $J$ = current density ($\text{MA/cm}^2$) - $n \approx 2$ (current exponent) - $E_a \approx 0.7-0.9 \text{ eV}$ (Cu) **Current Density Limit:** $$ J_{max} \approx 1-2 \text{ MA/cm}^2 \quad \text{(Cu at 105°C)} $$ ### 18.4 Packing & Ship **Tape & Reel:** - Components in carrier tape - 8mm, 12mm, 16mm tape widths - Standard reel: 7" or 13" **Tray Packing:** - JEDEC standard trays - For larger packages **Moisture Sensitivity Level (MSL):** | MSL | Floor Life | Storage | |-----|------------|---------| | 1 | Unlimited | Ambient | | 2 | 1 year | $< 60\%$ RH | | 3 | 168 hrs | Dry pack | | 4 | 72 hrs | Dry pack | | 5 | 48 hrs | Dry pack | | 6 | 6 hrs | Dry pack | ## Technology Scaling ### Moore's Law $$ N_{transistors} = N_0 \cdot 2^{t/T_2} $$ Where $T_2 \approx 2 \text{ years}$ (doubling time) ### Node Naming vs. Physical Dimensions | "Node" | Gate Pitch | Metal Pitch | Fin Pitch | |--------|------------|-------------|-----------| | 14nm | $70 \text{ nm}$ | $52 \text{ nm}$ | $42 \text{ nm}$ | | 10nm | $54 \text{ nm}$ | $36 \text{ nm}$ | $34 \text{ nm}$ | | 7nm | $54 \text{ nm}$ | $36 \text{ nm}$ | $30 \text{ nm}$ | | 5nm | $48 \text{ nm}$ | $28 \text{ nm}$ | $25-30 \text{ nm}$ | | 3nm | $48 \text{ nm}$ | $21 \text{ nm}$ | GAA | ### Transistor Density $$ \rho_{transistor} = \frac{N_{transistors}}{A_{die}} \quad [\text{MTr/mm}^2] $$ | Node | Density (MTr/mm²) | |------|-------------------| | 14nm | $\sim 37$ | | 10nm | $\sim 100$ | | 7nm | $\sim 100$ | | 5nm | $\sim 170$ | | 3nm | $\sim 300$ | ## Key Equations | Process | Equation | |---------|----------| | Oxidation (Deal-Grove) | $x^2 + Ax = B(t + \tau)$ | | Lithography Resolution | $CD = k_1 \cdot \frac{\lambda}{NA}$ | | Depth of Focus | $DOF = k_2 \cdot \frac{\lambda}{NA^2}$ | | Implant Profile | $N(x) = \frac{\Phi}{\sqrt{2\pi}\Delta R_p}\exp\left[-\frac{(x-R_p)^2}{2\Delta R_p^2}\right]$ | | Diffusion | $L_D = 2\sqrt{Dt}$ | | CMP (Preston) | $MRR = K_p \cdot P \cdot V$ | | Electroplating (Faraday) | $m = \frac{ItM}{nF}$ | | Yield (Poisson) | $Y = e^{-D_0 A}$ | | Thermal Resistance | $R_{th} = \frac{t}{kA}$ | | Electromigration (Black) | $MTTF = AJ^{-n}e^{E_a/k_BT}$ |
Show moisture exposure.
Direct metal-metal bonding at fine pitch.
Simultaneous oxide and metal bonding.
Stacked DRAM with logic die.
Combine multiple metrology techniques for better accuracy.
Combine multiple measurement techniques.
Spatially-resolved luminescence spectroscopy.
Current-voltage characteristic.
Achieving solution in inverse lithography.
Measure overlay from actual pattern images.
Fill space between lens and wafer with water to improve resolution.
Measure impurity distribution.
Measurements taken during processing to monitor and control.
Real-time monitoring during processing.
Real-time TEM during processing.
Cavity not fully filled.
Solution-based trace analysis.
TSMC's fan-out wafer-level packaging.
Use IR to see through wafer.
Ellipsometry in mid-IR range.
Inject liquid compound into mold.
Mark with ink.
Check wafers during processing.
Inline metrology correlates process measurements with final yield identifying contributing factors.
Improved DPC for light element imaging.
Built-in metrology in process tools.
Species affecting target measurement.
Compounds at bond interface.
Industry roadmap (historical).
Silicon or organic substrate connecting multiple dies.
Computationally design optimal mask patterns.
Measure unoccupied states.
# Inverse Problems 1. Introduction to Inverse Problems 1.1 Mathematical Definition In mathematical terms, a forward problem is defined as: $$ y = f(x) $$ where: - $x$ = input parameters (process conditions) - $f$ = forward operator (physical model) - $y$ = output observations (measurements, wafer state) The inverse problem seeks to find $x$ given $y$: $$ x = f^{-1}(y) $$ 1.2 Hadamard Well-Posedness Criteria A problem is well-posed if it satisfies: 1. Existence : A solution exists for all admissible data 2. Uniqueness : The solution is unique 3. Stability : The solution depends continuously on the data Most semiconductor inverse problems are ill-posed , violating one or more criteria. 1.3 Why Semiconductor Manufacturing Creates Ill-Posed Problems - Non-uniqueness : Multiple process conditions $\{x_1, x_2, \ldots\}$ can produce indistinguishable outputs within measurement precision - Sensitivity : Small perturbations in measurements cause large changes in estimated parameters: $$ \|x_1 - x_2\| \gg \|y_1 - y_2\| $$ - Incomplete information : Not all relevant physical quantities can be measured 2. Lithography Inverse Problems 2.1 Optical Proximity Correction (OPC) 2.1.1 Forward Model The aerial image intensity at the wafer plane: $$ I(x, y) = \left| \int \int H(f_x, f_y) \cdot M(f_x, f_y) \cdot e^{i2\pi(f_x x + f_y y)} \, df_x \, df_y \right|^2 $$ where: - $H(f_x, f_y)$ = optical transfer function (pupil function) - $M(f_x, f_y)$ = Fourier transform of the mask pattern - $(f_x, f_y)$ = spatial frequencies 2.1.2 Inverse Problem Formulation Find mask pattern $M$ that minimizes: $$ \mathcal{L}(M) = \|T(M) - D\|^2 + \lambda R(M) $$ where: - $T(M)$ = printed pattern from mask $M$ - $D$ = desired (target) pattern - $R(M)$ = regularization for mask manufacturability - $\lambda$ = regularization weight 2.1.3 Regularization Terms Common regularization terms include: - Mask complexity penalty : $$ R_{\text{complexity}}(M) = \int |\nabla M|^2 \, dA $$ - Minimum feature size constraint : $$ R_{\text{MFS}}(M) = \sum_i \max(0, w_{\min} - w_i)^2 $$ - Sidelobe suppression : $$ R_{\text{SRAF}}(M) = \int_{\Omega_{\text{dark}}} I(x,y)^2 \, dA $$ 2.2 Source-Mask Optimization (SMO) Joint optimization over source shape $S$ and mask $M$: $$ \min_{S, M} \|T(S, M) - D\|^2 + \lambda_1 R_S(S) + \lambda_2 R_M(M) $$ This is a higher-dimensional inverse problem with: - Source degrees of freedom: pupil discretization points - Mask degrees of freedom: pixel-based mask representation - Coupled nonlinear interactions 2.3 Inverse Lithography Technology (ILT) Full pixel-based mask optimization using gradient descent: $$ M^{(k+1)} = M^{(k)} - \alpha \nabla_M \mathcal{L}(M^{(k)}) $$ Gradient computation via adjoint method : $$ \nabla_M \mathcal{L} = \text{Re}\left\{ \mathcal{F}^{-1}\left[ H^* \cdot \mathcal{F}\left[ \frac{\partial \mathcal{L}}{\partial I} \cdot \psi^* \right] \right] \right\} $$ where $\psi$ is the complex field at the wafer plane. 3. Thin Film Metrology Inverse Problems 3.1 Ellipsometry 3.1.1 Measured Quantities Ellipsometry measures the complex reflectance ratio: $$ \rho = \frac{r_p}{r_s} = \tan(\Psi) \cdot e^{i\Delta} $$ where: - $r_p$ = p-polarized reflection coefficient - $r_s$ = s-polarized reflection coefficient - $\Psi$ = amplitude ratio angle - $\Delta$ = phase difference 3.1.2 Forward Model (Fresnel Equations) For a single film on substrate: $$ r_{012} = \frac{r_{01} + r_{12} e^{-i2\beta}}{1 + r_{01} r_{12} e^{-i2\beta}} $$ where: - $r_{01}, r_{12}$ = interface Fresnel coefficients - $\beta = \frac{2\pi d}{\lambda} \tilde{n}_1 \cos\theta_1$ = phase thickness - $d$ = film thickness - $\tilde{n}_1 = n_1 + ik_1$ = complex refractive index 3.1.3 Inverse Problem Given measured $\Psi(\lambda), \Delta(\lambda)$, find: - Film thickness(es): $d_1, d_2, \ldots$ - Optical constants: $n(\lambda), k(\lambda)$ for each layer Objective function : $$ \chi^2 = \sum_{\lambda} \left[ \left(\frac{\Psi_{\text{meas}} - \Psi_{\text{calc}}}{\sigma_\Psi}\right)^2 + \left(\frac{\Delta_{\text{meas}} - \Delta_{\text{calc}}}{\sigma_\Delta}\right)^2 \right] $$ 3.2 Scatterometry (Optical Critical Dimension) 3.2.1 Forward Model Rigorous Coupled-Wave Analysis (RCWA) solves Maxwell's equations for periodic structures: $$ \nabla \times \mathbf{E} = -\frac{\partial \mathbf{B}}{\partial t}, \quad \nabla \times \mathbf{H} = \frac{\partial \mathbf{D}}{\partial t} $$ The grating is represented as Fourier series: $$ \varepsilon(x, z) = \sum_m \varepsilon_m(z) e^{imGx} $$ where $G = \frac{2\pi}{\Lambda}$ is the grating vector. 3.2.2 Profile Parameterization A trapezoidal line profile is characterized by: - CD (Critical Dimension) : $w$ - Height : $h$ - Sidewall Angle : $\theta_{\text{SWA}}$ - Corner Rounding : $r$ - Footing/Undercut : $\delta$ Parameter vector: $\mathbf{p} = [w, h, \theta_{\text{SWA}}, r, \delta, \ldots]^T$ 3.2.3 Inverse Problem $$ \hat{\mathbf{p}} = \arg\min_{\mathbf{p}} \sum_{\lambda, \theta} \left( R_{\text{meas}}(\lambda, \theta) - R_{\text{RCWA}}(\lambda, \theta; \mathbf{p}) \right)^2 $$ Challenges : - Non-convex objective with multiple local minima - Parameter correlations (e.g., height vs. refractive index) - Sensitivity varies dramatically across parameters 4. Plasma Etch Inverse Problems 4.1 Etch Rate Modeling 4.1.1 Ion-Enhanced Etching Model $$ \text{ER} = k_0 \cdot \Gamma_{\text{ion}}^a \cdot \Gamma_{\text{neutral}}^b \cdot \exp\left(-\frac{E_a}{k_B T}\right) $$ where: - $\Gamma_{\text{ion}}$ = ion flux - $\Gamma_{\text{neutral}}$ = neutral radical flux - $E_a$ = activation energy - $a, b$ = reaction orders 4.1.2 Aspect Ratio Dependent Etching (ARDE) Etch rate in high-aspect-ratio features: $$ \text{ER}(AR) = \text{ER}_0 \cdot \frac{1}{1 + \alpha \cdot AR^\beta} $$ where $AR = \frac{\text{depth}}{\text{width}}$ is the aspect ratio. 4.2 Profile Reconstruction from OES 4.2.1 Optical Emission Spectroscopy Model Emission intensity for species $j$: $$ I_j(\lambda) = A_j \cdot n_e \cdot n_j \cdot \langle \sigma v \rangle_{j}^{\text{exc}} $$ where: - $n_e$ = electron density - $n_j$ = species density - $\langle \sigma v \rangle$ = rate coefficient for excitation 4.2.2 Inverse Problem From observed $I_j(t)$ time traces, determine: - Etch front position $z(t)$ - Layer interfaces - Process endpoint State estimation formulation : $$ \hat{z}(t) = \arg\min_{z} \|I_{\text{obs}}(t) - I_{\text{model}}(z, t)\|^2 + \lambda \left\|\frac{dz}{dt}\right\|^2 $$ 5. Ion Implantation Inverse Problems 5.1 As-Implanted Profile 5.1.1 LSS Theory (Lindhard-Scharff-Schiøtt) The implanted concentration profile: $$ C(x) = \frac{\Phi}{\sqrt{2\pi} \Delta R_p} \exp\left[-\frac{(x - R_p)^2}{2(\Delta R_p)^2}\right] $$ where: - $\Phi$ = implant dose (ions/cm²) - $R_p$ = projected range - $\Delta R_p$ = straggle (standard deviation) 5.1.2 Dual-Pearson for Channeling For crystalline substrates with channeling: $$ C(x) = (1-f) \cdot P_1(x; R_{p1}, \Delta R_{p1}, \gamma_1, \beta_1) + f \cdot P_2(x; R_{p2}, \Delta R_{p2}, \gamma_2, \beta_2) $$ where $P_i$ are Pearson IV distributions and $f$ is the channeled fraction. 5.2 Diffusion Inversion 5.2.1 Fick's Second Law with Concentration Dependence $$ \frac{\partial C}{\partial t} = \frac{\partial}{\partial x}\left[D(C) \frac{\partial C}{\partial x}\right] $$ For dopants like boron: $$ D(C) = D_i^* \left[1 + \beta_1 \left(\frac{C}{n_i}\right) + \beta_2 \left(\frac{C}{n_i}\right)^2\right] $$ 5.2.2 Inverse Problem Given final SIMS profile $C_{\text{final}}(x)$, find: - Initial implant conditions: $\Phi, E$ (energy) - Anneal conditions: $T(t)$, time $t_a$ - Diffusion parameters: $D_i^*, \beta_1, \beta_2$ Regularized formulation : $$ \min_{\theta} \|C_{\text{SIMS}} - C_{\text{simulated}}(\theta)\|^2 + \lambda \|\theta - \theta_{\text{prior}}\|^2 $$ 6. Deposition Inverse Problems 6.1 CVD Step Coverage 6.1.1 Thiele Modulus Conformality characterized by: $$ \phi = L \sqrt{\frac{k_s}{D_{\text{Kn}}}} $$ where: - $L$ = feature depth - $k_s$ = surface reaction rate - $D_{\text{Kn}}$ = Knudsen diffusion coefficient Step coverage: $$ SC = \frac{1}{\cosh(\phi)} $$ 6.1.2 Inverse Problem Given target step coverage $SC_{\text{target}}$, find: - Pressure $P$ - Temperature $T$ - Precursor partial pressures - Carrier gas flow 6.2 ALD Thickness Control 6.2.1 Growth Per Cycle (GPC) $$ \text{GPC} = \Theta_{\text{sat}} \cdot d_{\text{ML}} $$ where: - $\Theta_{\text{sat}}$ = saturation coverage (0 to 1) - $d_{\text{ML}}$ = monolayer thickness 6.2.2 Inverse Problem For target thickness $d$: $$ N_{\text{cycles}} = \left\lceil \frac{d}{\text{GPC}(T, t_{\text{pulse}}, t_{\text{purge}})} \right\rceil $$ Optimize $(T, t_{\text{pulse}}, t_{\text{purge}})$ for throughput and uniformity. 7. CMP Inverse Problems 7.1 Preston Equation Material removal rate: $$ \text{MRR} = K_p \cdot P \cdot V $$ where: - $K_p$ = Preston coefficient - $P$ = applied pressure - $V$ = relative velocity 7.2 Pattern Density Effects 7.2.1 Effective Density Model Local removal rate depends on pattern density $\rho$: $$ \text{MRR}_{\text{local}} = \frac{\text{MRR}_{\text{blanket}}}{\rho + (1-\rho) \cdot \eta} $$ where $\eta$ is the selectivity ratio. 7.2.2 Dishing and Erosion - Dishing (over-polish of metal in trench): $$ D = K_d \cdot w \cdot t_{\text{over}} $$ - Erosion (over-polish of dielectric): $$ E = K_e \cdot \rho \cdot t_{\text{over}} $$ 7.3 Inverse Problem Given target post-CMP topography, find: - Polish time - Pressure profile (zone control) - Slurry chemistry - Potentially: design rule modifications for pattern density 8. TCAD Parameter Extraction 8.1 Device Model MOSFET drain current: $$ I_D = \mu_{\text{eff}} C_{\text{ox}} \frac{W}{L} \left[(V_{GS} - V_{th})V_{DS} - \frac{V_{DS}^2}{2}\right] (1 + \lambda V_{DS}) $$ 8.2 Inverse Problem Formulation Given measured $I_D(V_{GS}, V_{DS})$ characteristics, extract: - $V_{th}$ = threshold voltage - $\mu_{\text{eff}}$ = effective mobility - $L_{\text{eff}}$ = effective channel length - $\lambda$ = channel length modulation Optimization : $$ \min_{\theta} \sum_{i,j} \left( I_{D,\text{meas}}(V_{GS,i}, V_{DS,j}) - I_{D,\text{model}}(V_{GS,i}, V_{DS,j}; \theta) \right)^2 $$ 8.3 Interface Trap Density from C-V From measured capacitance $C(V_G)$: $$ D_{it}(E) = \frac{1}{qA}\left(\frac{1}{C_{\text{meas}}} - \frac{1}{C_{\text{ox}}}\right)^{-1} - \frac{C_s}{qA} $$ where $C_s$ is the semiconductor capacitance. 9. Mathematical Solution Approaches 9.1 Regularization Methods 9.1.1 Tikhonov Regularization $$ \hat{x} = \arg\min_x \|Ax - y\|^2 + \lambda\|Lx\|^2 $$ Closed-form solution: $$ \hat{x} = (A^T A + \lambda L^T L)^{-1} A^T y $$ 9.1.2 Total Variation Regularization $$ \min_x \|Ax - y\|^2 + \lambda \int |\nabla x| \, dA $$ Preserves edges while smoothing noise. 9.1.3 L1 Regularization (LASSO) $$ \min_x \|Ax - y\|^2 + \lambda\|x\|_1 $$ Promotes sparse solutions. 9.2 Bayesian Inference 9.2.1 Posterior Distribution By Bayes' theorem: $$ p(x|y) = \frac{p(y|x) \cdot p(x)}{p(y)} \propto p(y|x) \cdot p(x) $$ where: - $p(y|x)$ = likelihood - $p(x)$ = prior - $p(x|y)$ = posterior 9.2.2 Maximum A Posteriori (MAP) Estimate $$ \hat{x}_{\text{MAP}} = \arg\max_x p(x|y) = \arg\max_x [\log p(y|x) + \log p(x)] $$ For Gaussian likelihood and prior: $$ \hat{x}_{\text{MAP}} = \arg\min_x \left[\frac{\|y - Ax\|^2}{2\sigma_n^2} + \frac{\|x - x_0\|^2}{2\sigma_x^2}\right] $$ This recovers Tikhonov regularization with $\lambda = \frac{\sigma_n^2}{\sigma_x^2}$. 9.3 Adjoint Methods for Gradient Computation For objective $\mathcal{L}(x) = \|F(x) - y\|^2$ with expensive forward model $F$: Forward solve : $$ F(x) = y_{\text{sim}} $$ Adjoint solve : $$ \left(\frac{\partial F}{\partial u}\right)^T \lambda = \frac{\partial \mathcal{L}}{\partial u} $$ Gradient : $$ \nabla_x \mathcal{L} = \left(\frac{\partial F}{\partial x}\right)^T \lambda $$ Computational cost: $O(1)$ forward + adjoint solves regardless of parameter dimension. 9.4 Machine Learning Approaches 9.4.1 Neural Network Surrogate Models Train $\hat{F}_\theta(x) \approx F(x)$: $$ \theta^* = \arg\min_\theta \sum_i \|F(x_i) - \hat{F}_\theta(x_i)\|^2 $$ Then use $\hat{F}_\theta$ for fast inverse optimization. 9.4.2 Physics-Informed Neural Networks (PINNs) Loss function includes physics residual: $$ \mathcal{L} = \mathcal{L}_{\text{data}} + \lambda_{\text{PDE}} \mathcal{L}_{\text{PDE}} + \lambda_{\text{BC}} \mathcal{L}_{\text{BC}} $$ where: $$ \mathcal{L}_{\text{PDE}} = \left\|\mathcal{N}[u_\theta(x,t)]\right\|^2 $$ for PDE operator $\mathcal{N}$. 10. Key Challenges and Considerations 10.1 Non-Uniqueness - Definition : Multiple solutions $\{x_1, x_2, \ldots\}$ satisfy $\|F(x_i) - y\| < \epsilon$ - Mitigation : Additional measurements, physical constraints, regularization - Quantification : Null space analysis, condition number $\kappa(A) = \frac{\sigma_{\max}}{\sigma_{\min}}$ 10.2 High Dimensionality - Parameter space : $\dim(x) \sim 10^2$ to $10^6$ (e.g., ILT masks) - Curse of dimensionality : Sampling density scales as $N^d$ - Approaches : Dimensionality reduction, sparse representations, hierarchical models 10.3 Computational Cost - Forward model cost : RCWA: $O(N^3)$ per wavelength; TCAD: hours for full 3D - Inverse iterations : Typically $10^2$ to $10^4$ forward evaluations - Mitigation : Surrogate models, multi-fidelity methods, parallel computing 10.4 Model Uncertainty - Sources : Unmodeled physics, parameter drift, measurement bias - Impact : Inverse solution may fit model but not reality - Approaches : Model calibration, uncertainty propagation, robust optimization 11. Emerging Directions 11.1 Digital Twins - Real-time state estimation combining physics models with sensor data - Kalman filtering for dynamic process tracking: $$ \hat{x}_{k|k} = \hat{x}_{k|k-1} + K_k(y_k - H\hat{x}_{k|k-1}) $$ 11.2 Multi-Fidelity Methods - Hierarchy of models: analytical → reduced-order → full numerical - Efficient exploration with cheap models, refinement with expensive ones - Multi-fidelity Gaussian processes for Bayesian optimization 11.3 Uncertainty Quantification - Full posterior distributions, not just point estimates - Sensitivity analysis: which measurements reduce uncertainty most? - Propagation to downstream process steps and device performance 11.4 End-to-End Differentiable Simulation - Automatic differentiation through entire process flow - Enables gradient-based optimization across traditionally separate steps - Requires differentiable forward models 12. Summary | Process Step | Forward Problem | Inverse Problem | |------------------|---------------------|---------------------| | Lithography | Mask → Printed pattern | Target pattern → Optimal mask | | Ellipsometry | Stack parameters → $\Psi, \Delta$ | $\Psi, \Delta$ → Thickness, n, k | | Scatterometry | Profile → Diffraction spectrum | Spectrum → Profile dimensions | | Plasma Etch | Recipe → Etch profile | Target profile → Recipe | | Ion Implant | Dose, energy → Dopant profile | Target profile → Implant conditions | | CVD/ALD | Recipe → Film properties | Target properties → Recipe | | CMP | Recipe, pattern → Final topography | Target topography → Recipe | | TCAD | Process/device params → I-V curves | I-V curves → Extracted parameters |