Compound
semiconductor, GaAs, InP, devices
Wide bandgap (WBG) power semiconductors, gallium nitride (GaN) High-Electron-Mobility Transistors (HEMT), and silicon carbide (4H-SiC) power MOSFETs constitute the foundational…
3,533 technical terms and definitions
semiconductor, GaAs, InP, devices
Wide bandgap (WBG) power semiconductors, gallium nitride (GaN) High-Electron-Mobility Transistors (HEMT), and silicon carbide (4H-SiC) power MOSFETs constitute the foundational…
indium phosphide inp, gaas device, iii-v integration silicon, heterogeneous material
Wide bandgap (WBG) power semiconductors, gallium nitride (GaN) High-Electron-Mobility Transistors (HEMT), and silicon carbide (4H-SiC) power MOSFETs constitute the foundational…
GaAs InP heterostructure, III-V epitaxy MBE MOCVD, indium gallium arsenide InGaAs, III-V photonic optoelectronic device
Wide bandgap (WBG) power semiconductors, gallium nitride (GaN) High-Electron-Mobility Transistors (HEMT), and silicon carbide (4H-SiC) power MOSFETs constitute the foundational…
iii v semiconductor, indium gallium arsenide, ingaas hemt, compound semiconductor foundry
Wide bandgap (WBG) power semiconductors, gallium nitride (GaN) High-Electron-Mobility Transistors (HEMT), and silicon carbide (4H-SiC) power MOSFETs constitute the foundational…
packaging
Compression molding is the encapsulation method that cures molding compound by compressing material directly over package arrays in a closed mold - it is widely used for thin…
computational lithography, device modeling, semiconductor simulation, pde, ilt, opc
Semiconductor Manufacturing: Computational Challenges Overview Semiconductor manufacturing represents one of the most mathematically and computationally intensive industrial…
ilt inverse lithography, smo source mask optimization, curvilinear mask, gpu computational lithography, opc
Computational Lithography and Optical Proximity Correction constitute the mathematical and algorithmic backbone of sub-wavelength semiconductor patterning. Operating deep within…
computational lithography runtime prediction, computational lithography runtime, lithography runtime prediction, computational lithography, lithography runtime, runtime prediction
Computational Lithography Runtime Prediction with Machine Learning Introduction & Motivation Computational Lithography Runtime Prediction with Machine Learning addresses a central…
image classification, object detection, image segmentation, vision transformer, wafer inspection
computer vision is the field that enables machines to extract structure, identity, geometry, motion, and meaning from images and video. It drives inspection, autonomy, robotics…
metrology
Conductive AFM (C-AFM) is a scanning probe microscopy technique that simultaneously maps surface topography and local electrical conductivity by applying a DC bias between…
packaging
Conductive vs static-dissipative packaging is the comparison of packaging materials that either rapidly conduct charge away or slowly dissipate charge to control ESD risk…
metrology
Confocal microscopy is an optical imaging technique that uses a pinhole aperture to reject out-of-focus light, enabling high-resolution 3D imaging and surface profiling…
ALD, CVD, techniques
Conformal Film Deposition ALD vs CVD is a critical comparison of two film deposition techniques used throughout semiconductor manufacturing, each providing distinct advantages…
film conformality, conformality ratio, deposition conformality, sidewall coverage, cvd conformality, thin film conformality, high aspect ratio conformality, conformal coating, conformality measurement, cvd
Conformality is not a property of a deposition process. It is a property of a process, a feature, and a pressure considered together, and a conformality number quoted without…
reach, email, chip foundry, services, consulting
ChipFoundryServices helps teams turn semiconductor and AI questions into practical next steps, from early architecture choices to foundry-facing execution plans. The useful…
metrology
Contact Angle Measurement is the metrology technique that quantifies the wettability of a silicon wafer surface by measuring the angle formed at the three-phase contact line where…
metrology
Contact chain is a series of repeated contact holes for resistance testing — long strings of contacts between metal and silicon/poly layers that measure contact resistance…
interconnect predicting contact etch depth uniformity across the wafer, interconnect predicting contact, predicting contact etch, contact etch depth, etch depth uniformity, predicting contact
Interconnect: Predicting contact etch depth uniformity across the wafer Introduction & Motivation Interconnect: Predicting contact etch depth uniformity across the wafer addresses…
contact hole patterning, contact etch, contact resistance, contact fill, contact module, self-aligned contact, SAC, contact plug, MOL contact, lithography
A contact hole is not a shape. It is a vertical electrical path that happens to start as a shape, and the shape is the least interesting thing about it. Every integrated circuit…
metrology
Contact measurement is a metrology approach where a physical probe or stylus touches the sample surface to measure dimensions, topography, or material properties — providing…
specific contact resistance, contact resistivity, salicide contact, metal semiconductor contact, ohmic contact cmos
Self-aligned silicides and nanoscale contact metallization architectures represent the material and thermodynamic interfaces engineered to establish low-resistance ohmic…
specific contact resistivity, contact resistance, ohmic contact semiconductor, rc semiconductor, contact resistivity
Self-aligned silicides and nanoscale contact metallization architectures represent the material and thermodynamic interfaces engineered to establish low-resistance ohmic…
contact resistance at metal-semiconductor interface prediction, contact resistance metal-semiconductor, resistance metal-semiconductor interface
Contact Resistance at Metal-Semiconductor Interface Prediction with Machine Learning Introduction & Motivation Contact Resistance at Metal-Semiconductor Interface Prediction…
silicide contact advanced node, metal semiconductor contact, wrap around contact gaa, contact resistivity reduction
Self-aligned silicides and nanoscale contact metallization architectures represent the material and thermodynamic interfaces engineered to establish low-resistance ohmic…
silicide contact, contact scaling, metal semiconductor contact, ohmic contact cmos
Self-aligned silicides and nanoscale contact metallization architectures represent the material and thermodynamic interfaces engineered to establish low-resistance ohmic…
airborne molecular contamination, amc, cleanroom chemistry, contamination sources
Semiconductor cleanroom engineering, ultra-pure water synthesis, and advanced facility distribution networks constitute the critical physical infrastructure required to sustain…
cooling solution design for chiplet stacking and heat extraction, cooling solution design, solution design chiplet, design chiplet stacking, chiplet stacking heat, cooling solution
Cooling Solution Design for Chiplet Stacking and Heat Extraction Introduction & Motivation Cooling Solution Design for Chiplet Stacking and Heat Extraction addresses a central…
coordinate measuring machine, cmm, metrology
Coordinate Measuring Machine (CMM) is a precision 3D measurement system that determines the geometry of physical objects by probing discrete points on their surfaces — used…
packaging
Coplanarity is the degree to which package leads or contact surfaces lie in the same geometric plane - it is a critical parameter for reliable solder-joint formation during board…
cu electroplating, copper plating, damascene plating, copper seed layer, electrochemical deposition, ecd copper
Copper dual damascene interconnect architectures, electrochemical superfilling, and barrier-seed metallization constitute the back-end-of-line (BEOL) wiring systems that route…
Cu ECD, electrochemical deposition, damascene plating
Copper dual damascene interconnect architectures, electrochemical superfilling, and barrier-seed metallization constitute the back-end-of-line (BEOL) wiring systems that route…
cu bonding, wire bond, gold wire bonding, forming gas, free air ball, thermosonic bonding, packaging cost reduction, bond pad damage, capillary tooling
Copper wire bonding is a packaging interconnect technique that uses fine copper wire, instead of gold, to connect a chip's bond pads to its package leads — a swap driven almost…
corona charge deposition uniformity prediction machine learning, corona charge, deposition uniformity prediction, corona charge deposition uniformity prediction
Corona Charge Deposition Uniformity Prediction with Machine Learning Introduction & Motivation Corona Charge Deposition Uniformity Prediction with Machine Learning addresses…
metrology
Corona-Kelvin metrology substitutes a controlled deposit of calibrated ionic charge for a conventional metal-oxide-semiconductor (MOS) gate electrode, enabling noncontact…
metrology
Correctables and Residuals in overlay metrology are the two components of the total overlay error — correctables are systematic, repeatable errors that can be modeled and fed back…
metrology
Spectroscopic ellipsometry and inline optical wafer metrology constitute the non-destructive physical measurement and defect detection disciplines that govern yield control across…
semiconductor economics, manufacturing cost, wafer cost, die cost, yield economics, fab economics, hbm4 cost and economics, hbm4 stack cost per bit
Semiconductor Manufacturing Process Cost Modeling Overview Semiconductor cost modeling quantifies the expenses of fabricating integrated circuits—from raw wafer to tested die. It…
industry
Cost per wafer is the total manufacturing cost to process one wafer through all fabrication steps. It's the fundamental unit economics metric for semiconductor manufacturing.…
packaging
Cover tape is the sealing film applied over carrier tape pockets to retain components until feeder peel-back at placement - it protects parts during transport while enabling…
metrology
Coverage Factor ( ) is the multiplier applied to the combined standard uncertainty to obtain the expanded uncertainty — , chosen to provide a specified level of confidence…
cowos chip on wafer on substrate, chip-on-wafer-on-substrate, advanced packaging, silicon interposer, hbm packaging
Interposers are the substrates that carry 2.5D integration: a die-to-die wiring layer dense enough to route thousands of connections between chiplets that sit side by side.…
cowos and 3d packaging, cowos packaging, cowos, cowos & emib, cowos and emib, cowos-s, cowos-l, cowos-r, advanced 3d packaging, silicon interposer, 3d hybrid bonding, tsmc cowos
CoWoS & 3D Packaging: Advanced 2.5D/3D Heterogeneous Integration, Sub-Micron Interconnect Physics, and the Packaging Toll Bridge Moat CoWoS (Chip-on-Wafer-on-Substrate) and 3D…
CoWoS, TSMC CoWoS, CoWoS-S, CoWoS-R, CoWoS-L, chip on wafer on substrate
CoWoS technology. is TSMC’s Chip-on-Wafer-on-Substrate family for integrating logic dies, chiplets, and high-bandwidth memory in large 2.5D packages. In the canonical CoWoS-S…
cd-afm, metrology, boot-shaped tip, re-entrant sidewall, tip shape calibration, tip wear, characterization grating, NIST traceable, OCD calibration reference
Critical dimension AFM (CD-AFM) measures the width, height, and sidewall shape of semiconductor features by physically tracing a specially-shaped probe tip across the feature's…
critical dimension, cd, lithography
Critical dimension (CD) is the measurable width of a patterned feature that must be controlled closely because it directly sets the electrical behavior of the device.…
cd metrology sem, cd uniformity across wafer, line width roughness lwr, cd-sem measurement, euv stochastics
Critical Dimension Control Critical dimension (CD) control is the measurement-and-control discipline used to keep patterned feature dimensions within functional limits from mask…
cd-saxs, cdsaxs, critical dimension saxs, cd-saxs metrology, x-ray critical dimension metrology
Critical-dimension small-angle X-ray scattering measures the average three-dimensional shape of periodic semiconductor structures by transmitting short-wavelength X-rays through…
cross-bridge kelvin resistor, cbkr, metrology
Cross-Bridge Kelvin Resistor (CBKR) measures contact resistance accurately — a specialized test structure that separates contact resistance from spreading resistance, enabling…
metrology
Cross-section preparation is the technique of cutting through a semiconductor device perpendicular to the wafer surface to expose its internal layer structure for microscopic…
metrology
Cross-section SEM images a cleaved or FIB-cut wafer edge to reveal layer structures, film thicknesses, feature profiles, and subsurface defects. Preparation: Cleave: Break wafer…