surface roughness measurement, metrology
Quantify surface irregularities (Ra Rq Rz).
923 technical terms and definitions
Quantify surface irregularities (Ra Rq Rz).
Enhanced Raman using nanostructures.
Use synchrotron for advanced X-ray analysis.
Integrate multiple dies or components in single package.
Repeating defect patterns.
Repeating pattern across wafers.
Standard widths 8mm 12mm 16mm etc.
ARC layer on top of resist.
Ultra-high resolution imaging for defect analysis.
Attach to carrier for processing.
Reversible bonding for processing.
Characterize carrier dynamics with THz.
Study preferred crystal orientations.
Separate via thermal differential.
Large thermal contact area.
Thermal test chips contain heating elements and temperature sensors for measuring thermal resistance.
Vias for heat transfer.
Bond using heat and pressure.
Use heated tool for bonding.
Alternative thin QFP.
Thin and fine pitch.
Thinner version of SOP.
3D reconstruction of doping.
Insert leads into PCB holes.
Via through interposer.
Expose TSV ends after thinning.
Duration solder is molten.
Predict future behavior.
Surface mass spectrometry.
Measure luminescence dynamics.
Measure carrier lifetime.
Nanoscale Raman with AFM tip.
Critical spacing between line ends.
Chemical imaging with SIMS.
Markings on package top.
SEM imaging from above to measure CD and patterns.
Surface metal contamination.
Maximum thickness difference on wafer.
Inject molding compound under pressure.
Pressure forcing compound.
Move calibration between locations.
See through thin samples at atomic scale.
EBSD on thin samples.
Components in matrix tray.
# TSMC vs Intel: Comprehensive Semiconductor Analysis ## Executive Summary The semiconductor foundry market represents one of the most critical and competitive sectors in global technology. This analysis examines the two primary players: | Company | Founded | Headquarters | Business Model | 2025 Foundry Market Share | |---------|---------|--------------|----------------|---------------------------| | **TSMC** | 1987 | Hsinchu, Taiwan | Pure-Play Foundry | ~67.6% | | **Intel** | 1968 | Santa Clara, USA | IDM → IDM 2.0 (Hybrid) | ~0.1% (external) | ## Business Model Comparison ### TSMC: Pure-Play Foundry Model - **Core Philosophy:** Manufacture chips exclusively for other companies - **Key Advantage:** No competition with customers → Trust - **Customer Base:** - Apple (~25% of revenue) - NVIDIA - AMD - Qualcomm - MediaTek - Broadcom - 500+ total customers ### Intel: IDM 2.0 Transformation - **Historical Model:** Integrated Device Manufacturer (design + manufacturing) - **Current Strategy:** Hybrid approach under "IDM 2.0" - Internal products: Intel CPUs, GPUs, accelerators - External foundry: Intel Foundry Services (IFS) - External sourcing: Using TSMC for some chiplets **Strategic Challenge:** Convincing competitors to trust Intel with sensitive chip designs ## Market Share & Financial Metrics ### Foundry Market Share Evolution ``` Q3 2024 → Q4 2024 → Q1 2025 ``` | Company | Q3 2024 | Q4 2024 | Q1 2025 | |---------|---------|---------|---------| | TSMC | 64.0% | 67.1% | 67.6% | | Samsung | 12.0% | 11.0% | 7.7% | | Others | 24.0% | 21.9% | 24.7% | ### Revenue Comparison (2025 Projection) The revenue disparity is stark: $$ \text{Revenue Ratio} = \frac{\text{TSMC Revenue}}{\text{Intel Foundry Revenue}} = \frac{\$101B}{\$120M} \approx 842:1 $$ Or approximately: $$ \text{TSMC Revenue} \approx 1000 \times \text{Intel Foundry Revenue} $$ ### Key Financial Metrics #### TSMC Financial Health - **Revenue (2025 YTD):** ~$101 billion (10 months) - **Gross Margin:** ~55-57% - **Capital Expenditure:** ~$30-32 billion annually - **R&D Investment:** ~8% of revenue $$ \text{TSMC CapEx Intensity} = \frac{\text{CapEx}}{\text{Revenue}} = \frac{32B}{120B} \approx 26.7\% $$ #### Intel Financial Challenges - **2024 Annual Loss:** $19 billion (first since 1986) - **Foundry Revenue (2025):** ~$120 million (external only) - **Workforce Reduction:** ~15% (targeting 75,000 employees) - **Break-even Target:** End of 2027 $$ \text{Intel Foundry Operating Loss} = \text{Revenue} - \text{Costs} < 0 \quad \text{(through 2027)} $$ ## Technology Roadmap ### Process Node Timeline ``` Year TSMC Intel ──────────────────────────────────────────────── 2023 N3 (3nm) Intel 4 2024 N3E, N3P Intel 3 2025 N2 (2nm) - GAA 18A (1.8nm) - GAA + PowerVia 2026 N2P, A16 18A-P 2027 N2X - 2028-29 A14 (1.4nm) 14A ``` ### Transistor Technology Evolution Both companies are transitioning from FinFET to Gate-All-Around (GAA): $$ \text{GAA Advantage} = \begin{cases} \text{Better electrostatic control} \\ \text{Reduced leakage current} \\ \text{Higher drive current per area} \end{cases} $$ #### TSMC N2 Specifications - **Transistor Density Increase:** +15% vs N3E - **Performance Gain:** +10-15% @ same power - **Power Reduction:** -25-30% @ same performance - **Architecture:** Nanosheet GAA $$ \Delta P_{\text{power}} = -\left(\frac{P_{N3E} - P_{N2}}{P_{N3E}}\right) \times 100\% \approx -25\% \text{ to } -30\% $$ #### Intel 18A Specifications - **Architecture:** RibbonFET (GAA variant) - **Unique Feature:** PowerVia (Backside Power Delivery Network) - **Target:** Competitive with TSMC N2/A16 **PowerVia Advantage:** $$ \text{Signal Routing Efficiency} = \frac{\text{Available Metal Layers (Front)}}{\text{Total Metal Layers}} \uparrow $$ By moving power delivery to the backside: $$ \text{Interconnect Density}_{\text{18A}} > \text{Interconnect Density}_{\text{N2}} $$ ## Manufacturing Process Comparison ### Yield Rate Analysis Yield rate ($Y$) is critical for profitability: $$ Y = \frac{\text{Good Dies}}{\text{Total Dies}} \times 100\% $$ **Current Status (2025):** | Process | Company | Yield Status | |---------|---------|--------------| | N2 | TSMC | Production-ready (~85-90% mature) | | 18A | Intel | ~10% (risk production, improving) | **Defect Density Model (Poisson):** $$ Y = e^{-D \cdot A} $$ Where: - $D$ = Defect density (defects/cm²) - $A$ = Die area (cm²) For a given defect density, larger dies have exponentially lower yields. ### Wafer Cost Economics **Cost per Transistor Scaling:** $$ \text{Cost per Transistor} = \frac{\text{Wafer Cost}}{\text{Transistors per Wafer}} $$ $$ \text{Transistors per Wafer} = \frac{\text{Wafer Area} \times Y}{\text{Die Area}} \times \text{Transistor Density} $$ **Approximate Wafer Costs (2025):** | Node | Wafer Cost (USD) | |------|------------------| | N3/3nm | ~$20,000 | | N2/2nm | ~$30,000 | | 18A | ~$25,000-30,000 (estimated) | ## AI & HPC Market Impact ### AI Chip Manufacturing Dominance TSMC manufactures virtually all leading AI accelerators: - **NVIDIA:** H100, H200, Blackwell (B100, B200, GB200) - **AMD:** MI300X, MI300A, MI400 (upcoming) - **Google:** TPU v4, v5, v6 - **Amazon:** Trainium, Inferentia - **Microsoft:** Maia 100 ### Advanced Packaging: The New Battleground **TSMC CoWoS (Chip-on-Wafer-on-Substrate):** $$ \text{HBM Bandwidth} = \text{Memory Channels} \times \text{Bus Width} \times \text{Data Rate} $$ For NVIDIA H100: $$ \text{Bandwidth}_{\text{H100}} = 6 \times 1024\text{ bits} \times 3.2\text{ Gbps} = 3.35\text{ TB/s} $$ **Intel Foveros & EMIB:** - **Foveros:** 3D face-to-face die stacking - **EMIB:** Embedded Multi-die Interconnect Bridge - **Foveros-B (2027):** Next-gen hybrid bonding $$ \text{Interconnect Density}_{\text{Hybrid Bonding}} \gg \text{Interconnect Density}_{\text{Microbump}} $$ ### AI Chip Demand Growth $$ \text{AI Chip Market CAGR} \approx 30-40\% \quad (2024-2030) $$ Projected market size: $$ \text{Market}_{2030} = \text{Market}_{2024} \times (1 + r)^6 $$ Where $r \approx 0.35$: $$ \text{Market}_{2030} \approx \$50B \times (1.35)^6 \approx \$300B $$ ## Geopolitical Considerations ### Taiwan Concentration Risk **TSMC Geographic Distribution:** | Location | Capacity Share | Node Capability | |----------|----------------|-----------------| | Taiwan | ~90% | All nodes (including leading edge) | | Arizona, USA | ~5% (growing) | N4, N3 (planned) | | Japan | ~3% | N6, N12, N28 | | Germany | ~2% (planned) | Mature nodes | **Risk Assessment Matrix:** $$ \text{Geopolitical Risk Score} = w_1 \cdot P(\text{conflict}) + w_2 \cdot \text{Supply Concentration} + w_3 \cdot \text{Substitutability}^{-1} $$ **Intel's Strategic Value Proposition:** $$ \text{National Security Value} = f(\text{Domestic Capacity}, \text{Technology Leadership}, \text{Supply Chain Resilience}) $$ ## Investment Analysis ### Valuation Metrics #### TSMC (NYSE: TSM) $$ \text{P/E Ratio}_{\text{TSMC}} \approx 25-30 \times $$ $$ \text{EV/EBITDA}_{\text{TSMC}} \approx 15-18 \times $$ #### Intel (NASDAQ: INTC) $$ \text{P/E Ratio}_{\text{INTC}} = \text{N/A (negative earnings)} $$ $$ \text{Price/Book}_{\text{INTC}} \approx 1.0-1.5 \times $$ ### Return on Invested Capital (ROIC) $$ \text{ROIC} = \frac{\text{NOPAT}}{\text{Invested Capital}} $$ | Company | ROIC (2024) | |---------|-------------| | TSMC | ~25-30% | | Intel | Negative | ### Break-Even Analysis for Intel Foundry Target: Break-even by end of 2027 $$ \text{Break-even Revenue} = \frac{\text{Fixed Costs}}{\text{Contribution Margin Ratio}} $$ Required conditions: 1. 18A yield improvement to >80% 2. EUV penetration increase (5% → 30%+) 3. External customer acquisition $$ \text{ASP Growth Rate} \approx 3 \times \text{Cost Growth Rate} $$ ### Critical Milestones to Watch 1. **Q4 2025:** Intel Panther Lake (18A) commercial launch 2. **2026:** TSMC N2 mass production ramp 3. **2026:** Intel 18A yield maturation 4. **2027:** Intel Foundry break-even target 5. **2028-29:** 14A/A14 generation competition ## Mathematical ### Moore's Law Scaling Traditional Moore's Law: $$ N(t) = N_0 \cdot 2^{t/T} $$ Where: - $N(t)$ = Transistor count at time $t$ - $N_0$ = Initial transistor count - $T$ = Doubling period (~2-3 years) **Current Reality:** $$ T_{\text{effective}} \approx 30-36 \text{ months} \quad \text{(slowing)} $$ ### Dennard Scaling (Historical) $$ \text{Power Density} = C \cdot V^2 \cdot f $$ Where: - $C$ = Capacitance (scales with feature size) - $V$ = Voltage - $f$ = Frequency **Post-Dennard Era:** Dennard scaling broke down ~2006. Power density no longer constant: $$ \frac{d(\text{Power Density})}{d(\text{Node})} > 0 \quad \text{(increasing)} $$ ### Amdahl's Law for Heterogeneous Computing $$ S = \frac{1}{(1-P) + \frac{P}{N}} $$ Where: - $S$ = Speedup - $P$ = Parallelizable fraction - $N$ = Number of processors/accelerators
Vertical electrical connection through wafer for 3D stacking.
Layers for TSV metallization.
Parasitic capacitance of TSV.
Fill TSV with metal.
Create through-silicon vias.