3,538 technical terms and definitions
hybrid bonding cu cu, wafer level bonding design, bonding pitch design rule, 3d ic bonding alignment, hybrid bonding
Hybrid bonding joins two wafers or dies by bonding copper pads and the surrounding dielectric at the same time, producing a metallurgical copper-to-copper connection with no…
die-to-wafer bonding particle entrapment prediction, die-to-wafer bonding particle, bonding particle entrapment, particle entrapment prediction, bonding particle
Die-to-Wafer Bonding Particle Entrapment Prediction with Machine Learning Introduction & Motivation Die-to-Wafer Bonding Particle Entrapment Prediction with Machine Learning…
die to wafer bonding throughput prediction with machine learning, die wafer bonding throughput prediction machine learning, die wafer, bonding throughput prediction
Die-to-Wafer Bonding Throughput Prediction with Machine Learning Introduction & Motivation Die-to-Wafer Bonding Throughput Prediction with Machine Learning addresses a central…
die-to-wafer hybrid bonding particle gap prediction, die-to-wafer hybrid bonding, hybrid bonding particle, bonding particle gap, particle gap prediction
Die-to-Wafer Hybrid Bonding Particle Gap Prediction with Machine Learning Introduction & Motivation Die-to-Wafer Hybrid Bonding Particle Gap Prediction with Machine Learning…
Process Selectivity, plasma etching
Dielectric Etch Process Selectivity is a critical semiconductor patterning process characteristic requiring excellent selectivity between etching the intended dielectric material…
dpc, dpc-stem, differential phase contrast stem, com dpc, center of mass dpc, semiconductor electric field microscopy
A semiconductor cross-section can look structurally perfect while its internal electrostatics are wrong. A junction may carry an unintended field, a polarization sheet may…
dbo, metrology, overlay target, diffraction order asymmetry, swing curve calibration, micro-DBO, tool-induced shift, TIS correction, sub-nanometer overlay
Diffraction-based overlay (DBO) is an optical metrology technique that measures how precisely two patterned layers line up with each other by analyzing the light diffracted off…
diffused base transistor 1954 wafer selection, radial resistivity gradient diffused base wafer, baseline doping guard band junction depth
Select Usable Crystal Sections: One Surface Has to Carry Both Junctions, So One Standard Has to Cover the Whole Section This step chooses which lengths of the inspected rod…
diffused base transistor 1954 slicing wafers, wafer thickness collector margin junction depth, kerf loss slicing yield diffused base
Slice the Germanium: A Thickness That Has to Outlast Two Diffusions and Still Leave a Collector This step cuts wafers from the sections Step 5 approved, and the thickness it…
diffused base transistor 1954 rinse furnace contamination, shared diffusion furnace ambient contamination risk, drying interval predeposition surface drift
Rinse and Dry: Residue Here Does Not Just Contaminate One Device, It Can Contaminate a Furnace Full of Them This step rinses and dries the etched wafer, and the stakes for getting…
diffused base transistor 1954 furnace boat loading, constant source boundary condition predeposition, multi wafer boat flux uniformity diffused base
Load the Wafer and Establish the Furnace Atmosphere: Setting Up the Boundary Condition Predeposition Will Depend On This step loads the verified wafer into the diffusion furnace…
diffused base transistor 1954 base predeposition dose, dose metering predeposition diffused base, sheet resistance checkpoint predeposition dose
Perform Base Predeposition: Metering a Dose This Process Will Spend the Rest of Its Schedule Protecting This step actually runs the base dopant's predeposition — holding the wafer…
diffused base transistor 1954 sheet resistance check, dose depth square root error propagation diffused base, in process checkpoint before drive in diffused base
Verify Base Predeposition Dose: Catching an Error Before It Disguises Itself as Something Else This step measures the sheet resistance of the predeposited layer and converts that…
diffused base transistor 1954 limited source seal, leaky seal constant source drive in diffused base, residual flux confirmation procedural discipline
Seal the Wafer for Drive-In: Making the Limited-Source Assumption Actually True This step removes the gas-phase dopant source and seals the furnace ambient around the wafer…
diffused base transistor 1954 groove and stain, witness wafer representativeness diffused base, junction depth measurement destructive technique
Verify Base-Collector Junction Depth: The First Hard Number This Entire Chain of Assumptions Has Produced This step measures where the base-collector junction actually landed…
diffused base transistor 1954 furnace tube memory, cross contamination opposite dopant diffused base, thermal budget accumulation base junction
Load for Emitter Predeposition: Protecting a Finished Junction While Preparing for Its Opposite This step loads the wafer into a furnace for the emitter dopant's predeposition…
diffused base transistor 1954 emitter dose metering, solid solubility curve opposite dopant species, emitter predeposition recipe diffused base
Perform Emitter Predeposition: Metering a Second Dose on a Wafer That Is No Longer a Blank Surface This step meters the emitter dopant's dose, , using the same constant-source…
diffused base transistor 1954 emitter dose check, thermal exposure bookkeeping base drift diffused base, two diffusion checkpoint sheet resistance
Verify Emitter Predeposition Dose: A Checkpoint That Now Has to Watch Two Diffusions at Once This step measures the emitter dose Step 18 actually delivered, using the same…
diffused-base transistor base predeposition, base predeposition diffusion, constant-source base predeposition, transistor base dopant predeposition, predeposition dosing diffused base transistor
Diffused-Base Transistor Base Predeposition: Constant-Source Dose Control Before Drive-In Base predeposition is the dopant-loading step that gives a diffused-base transistor…
diffused-base transistor process flow, diffused base transistor device process flow, double diffused base transistor, predeposition drive-in diffusion, erfc gaussian diffusion profile transistor
Diffused-Base Transistor Device Process Flow: Predeposition Dosing, Drive-In Profile Control & Double-Diffusion Yield The diffused-base transistor was the first transistor…
double diffusion transistor process, base emitter diffusion profile, fick law transistor junction depth, predeposition drive-in diffusion
Diffused Junction Transistor: Double-Diffusion Profiles & Why Depth Control Finally Reached Micrometers The diffused junction transistor replaced melt-and-refreeze alloying…
diffusion, ion implantation, dopant diffusion, fick law, implant profile, gaussian profile, pearson distribution, ted, transient enhanced diffusion, thermal budget, semiconductor doping
Mathematical Modeling of Diffusion and Ion Implantation in Semiconductor Manufacturing Part I: Diffusion Modeling Fundamental Equations Dopant redistribution in silicon…
fick laws, fick second law, semiconductor diffusion equations, dopant diffusion equations, arrhenius diffusion, junction depth calculation, transient enhanced diffusion, oxidation enhanced diffusion, numerical methods diffusion, thermal budget
Mathematical Modeling of Diffusion 1. Fundamental Governing Equations 1.1 Fick's Laws of Diffusion The foundation of diffusion modeling in semiconductor manufacturing rests on…
lithography
Diffusion length in photolithography refers to the average distance that chemically active species — primarily photoacid molecules in chemically amplified resists (CARs) — migrate…
diffusion model, fick law modeling, dopant diffusion model, semiconductor diffusion model, thermal diffusion model, diffusion coefficient calculation, diffusion simulation, diffusion mathematics
Mathematical Modeling of Diffusion in Semiconductor Manufacturing 1. Fundamental Governing Equations 1.1 Fick's Laws of Diffusion The foundation of diffusion modeling…
thermal diffusion, dopant diffusion
Diffusion — the thermal process by which dopant atoms migrate into a semiconductor lattice driven by concentration gradients, historically the primary doping method before ion…
digital manufacturing
Digital Twin of a Semiconductor Fab is a virtual replica of the entire fabrication facility — integrating physical models, equipment simulations, process recipes, logistics…
packaging
Dimensional tolerances is the allowable variation limits around nominal package dimensions that define acceptable manufacturing output - they set quantitative boundaries for fit…
advanced packaging
Direct Wafer Bonding (often referred to as Fusion Bonding) is the pinnacle of modern semiconductor substrate engineering, representing the miraculous physical and chemical process…
directed self-assembly, DSA lithography, block copolymer patterning, graphoepitaxy, chemoepitaxy
Directed self-assembly. uses the thermodynamic microphase separation of block copolymers to form dense nanoscale domains whose orientation and placement are constrained…
block copolymer lithography, dsa patterning, self assembly semiconductor, dsa defectivity
Directed Self-Assembly (DSA) is the next-generation patterning technique that uses the thermodynamic self-organization of block copolymer molecules to create sub-10 nm features…
block copolymer lithography, dsa grapho-epitaxy, bcp lamellar cylinder phase, dsa pattern placement error
Directed Self Assembly DSA Patterning is a materials-driven lithography technique exploiting block copolymer phase-separation physics to self-organize nanostructures at resolution…
block copolymer lithography, dsa patterning, self aligned patterning, bcp lithography, chemoepitaxy graphoepitaxy, flory huggins parameter
Directed Self-Assembly (DSA) of block copolymers (BCP) is the lithographic patterning technology that exploits thermodynamic microphase separation of diblock copolymer thin films…
block copolymer lithography, dsa pattern rectification, chemoepitaxy graphoepitaxy, sub-lithographic feature formation
Directed Self-Assembly DSA Patterning — Directed self-assembly leverages the thermodynamic self-organization of block copolymer materials to create sub-lithographic features…
metrology
Discrimination (or resolution) in metrology is the smallest change in a measured value that the measurement system can detect — the minimum increment that the gage can…
deep level transient spectroscopy, deep level spectroscopy, semiconductor trap spectroscopy, trap activation energy, defect characterization dlts
Deep-level transient spectroscopy identifies electrically active defects by watching a semiconductor junction return toward equilibrium after a controlled filling pulse.…
design of experiments, factorial design, semiconductor doe, rsm, response surface methodology, taguchi, robust parameter design
Design of Experiments (DOE) in Semiconductor Manufacturing DOE is a statistical methodology for systematically investigating relationships between process parameters and responses…
adapting models across different fabrication facilities, adapting models across, models across different, across different fabrication, different fabrication facilities, models across
Adapting models across different fabrication facilities Introduction & Motivation Adapting models across different fabrication facilities addresses a central problem in Machine…
n-type doping, p-type doping, dopant
Doping semiconductor is the controlled introduction of impurity atoms into a nearly pure crystal so engineers can set its electrical behavior. In silicon, this step is…
double diffused mesa transistor 1956 bell labs rca, drift field graded base silicon mesa transistor, shockley semiconductor nobel prize 1956 silicon transistor
The Double-Diffused Silicon Mesa Transistor: A Graded Base That Lets an Electric Field Do What Diffusion Alone Could Not In 1956, Bell Labs and RCA moved the double-diffusion…
smartnic, smart nic, data processing unit, infrastructure offload, dpu infrastructure offload chip, nvidia bluefield 3 dpu, amd pensando, nvme over fabrics
A DPU, or data processing unit, also sold as a SmartNIC, is the third class of processor in a modern datacenter, sitting alongside the CPU and the GPU. Where the CPU runs…
ECC DRAM, SECDED, Hamming code DRAM, Chipkill, Advanced ECC, ECC DIMM, single error correction double error detection
DRAM ECC: Hamming SECDED Architecture, Reliability Theory, and the Chipkill Application ECC is the layer that stops pretending the physics underneath it is perfect. Every…
dram cell structure, dram capacitor, dram refresh, 1t1c dram cell
DRAM (dynamic random-access memory) stores each bit as charge on a tiny capacitor, gated by a single access transistor — the '1T1C' cell. It is 'dynamic' because that charge leaks…
automated row stepping host triggers refresh generically, refresh overhead fraction r times t_rc over t_ret, responsibility moves to chip where retention physics lives
Let the Chip Remember Which Row Comes Next, So the System Does Not Have To 1. State What Manual Row-Stepping Would Demand of the Host System Step 4 established that a complete…
trench versus stacked capacitor dram 3d cell geometry, dram scaling substrate trench punchthrough vs stacked topography, 1t1c capacitor area perimeter height product third dimension
Step 2 — Choose Between Etching Down (Trench) and Building Up (Stacked): Two Geometries for the Third Dimension 1. The Fundamental Fork: Substrate Etching vs. Over-Gate…
deep reactive ion etch trench capacitor aspect ratio limits, dram trench sidewall capacitance scales with etch depth, aspect ratio dependent etching arde and void free fill dram
Step 3 — Build the Trench: Etch Depth as the New Area Budget 1. Sidewall Area Replaces Planar Pitch By cutting a high-aspect-ratio vertical cavity into the silicon substrate…
trench dram keyhole void pinch off knudsen diffusion limit, conformal lpcvd dielectric and polysilicon trench fill dram, step coverage aspect ratio dependent deposition dram yield
Step 7 — Fill the Trench Without Leaving a Void: Conformal Deposition and the Pinch-Off Limit 1. Knudsen Diffusion and the Threat of Premature Pinch-Off Once a high-aspect-ratio…
dennard scaling breakdown 3d capacitor evolution dram, trench vs stacked legacy 3d semiconductor architecture dram, when planar physics failed 3d dimension solved moore law
Step 10 — The 1974 Retrospective: When Leaving the Plane Became the Only Way Forward 1. The Immutable Circuit Law and the Collapse of Two Dimensions Robert Dennard’s 1968 1T1C…
drift-diffusion transport, drift-diffusion model, semiconductor carrier transport, drift diffusion equations, semiconductor continuity equations, quasi-fermi transport, TCAD drift diffusion
Drift–diffusion transport is the continuum model that converts electric fields, carrier-density gradients, generation, recombination, and contact injection into semiconductor…
metrology
Spectroscopic ellipsometry and inline optical wafer metrology constitute the non-destructive physical measurement and defect detection disciplines that govern yield control across…