449 technical terms and definitions
silicon wafer explained, semiconductor wafer meaning, wafer fabrication, what is a die vs wafer
A wafer is a thin, round slice of ultra-pure silicon — typically about 300 millimeters across on modern production lines — that serves as the base material on which an entire…
what is WAT semiconductor
A wafer acceptance test, or WAT, is a standardized set of electrical measurements taken on special test structures scattered across a wafer to confirm the underlying fabrication…
fab exhaust treatment, thermal abatement vs catalytic, hazardous process gas treatment, wet scrubbing vs abatement, greenhouse gas fab exhaust
Abatement is the treatment of a fab's process exhaust before it ever leaves the facility, and it exists because nearly every reactive chemical process covered throughout this…
ai accelerator chip explained, ai accelerator vs gpu, ai accelerator meaning, types of ai accelerators
An AI accelerator is any chip built specifically to speed up the math behind artificial intelligence — mostly large-scale matrix multiplication — rather than to handle…
integrated device manufacturer meaning, idm vs fabless, idm semiconductor company, what does idm mean in chips
An IDM, or Integrated Device Manufacturer, is a chip company that both designs its chips and manufactures them in its own fabrication plants — the opposite of the fabless model…
npu explained, neural processing unit, npu vs gpu vs cpu, on-device ai chip
An NPU, or Neural Processing Unit, is a chip or chip block built specifically to run the repetitive math behind neural networks — mostly large batches of matrix multiplication…
osat semiconductor meaning, outsourced assembly and test explained, osat vs foundry, chip packaging and testing company
An OSAT — short for Outsourced Semiconductor Assembly and Test — is a company that specializes in packaging finished silicon dies and testing completed chips, handling…
chip packaging explained, semiconductor packaging meaning, advanced packaging chiplets, what is a chip package
Chip packaging is the process of taking a finished, tested silicon die and encasing it in a protective housing with external connectors — the familiar black rectangle with metal…
chemical mechanical polishing explained, planarization semiconductor, cmp dishing erosion, copper damascene cmp, preston equation polishing
Chemical-Mechanical Polishing (CMP) is what flattens the wafer back out after deposition and etch leave it bumpy. Every layer built through the CVD-lithography-etch loop leaves…
compute in memory explained, in memory computing ai, compute in memory chip meaning, what does compute in memory mean
Compute-in-memory is a chip architecture approach that performs certain calculations directly inside memory itself, rather than following the traditional design of moving data out…
damascene process explained, dual damascene semiconductor, copper electroplating BEOL, barrier metal liner copper, low-k dielectric interconnect
Copper interconnect is the wiring that connects millions or billions of individual transistors into an actual working circuit. Once the transistors themselves are built through…
critical dimension explained, cd semiconductor meaning, critical dimension lithography, what does cd mean in chip manufacturing
Critical dimension, often abbreviated CD, refers to the smallest, most precisely controlled feature size on a chip — typically the width of the narrowest transistor gate or wire…
cryogenic plasma etch explained, high aspect ratio sidewall control, low temperature etch semiconductor, tsv etch profile, gaa release etch sidewall bowing
Cryo etch is plasma etching performed with the wafer cooled to extremely low temperatures, and it exists to solve an etch-profile problem that ordinary room-temperature…
chemical vapor deposition explained, CVD vs ALD semiconductor, PECVD LPCVD thermal CVD, step coverage conformality, thin film deposition chip fabrication
Chemical Vapor Deposition (CVD) is how a fab builds material up on the wafer instead of carving it away. Where plasma etch removes everything outside the mask, CVD does…
dof lithography explained, depth of focus meaning chip, lithography focus tolerance, dof semiconductor
Depth of focus, or DOF, is the vertical range above and below a lithography system's ideal focal plane within which a pattern can still be exposed sharply enough to be usable…
deep ultraviolet lithography explained, duv vs euv, duv lithography meaning, 193nm lithography
DUV, or deep ultraviolet lithography, is the workhorse lithography technology that patterned chips for decades before EUV arrived, using a longer wavelength of ultraviolet light…
euv lithography explained, extreme ultraviolet lithography meaning, how does euv work, euv chip manufacturing
EUV lithography is a chipmaking technique that uses extreme ultraviolet light — with a wavelength roughly fourteen times shorter than the light used in older lithography methods…
fabless company meaning, fabless vs idm, fabless semiconductor model, what does fabless mean
A fabless company designs chips but doesn't own or operate the factories that manufacture them, instead paying a foundry to fabricate its designs — a business model that lets…
flip chip explained, flip chip vs wire bonding, flip chip bonding meaning, what does flip chip mean
Flip chip packaging is a method of connecting a silicon die to its package by flipping the die upside down and attaching it directly via an array of tiny solder bumps across its…
hbm explained, hbm meaning ai chips, high bandwidth memory vs regular memory, what does hbm stand for
High bandwidth memory, or HBM, is a type of memory built by stacking multiple memory dies vertically and connecting them with extremely short, wide internal connections, achieving…
immersion lithography explained, water immersion lithography meaning, duv immersion, immersion lithography vs euv
Immersion lithography is a technique that places a thin layer of purified water between the lens and the wafer during DUV lithography, using water's optical properties to bend…
ion implantation explained, semiconductor doping process, boron phosphorus arsenic dopant, spike anneal activation, source drain junction implant
Ion implantation is how a fab actually changes silicon's electrical personality, not just its shape. Etch and CVD sculpt and build up physical structure, but neither one turns…
ler lithography explained, line edge roughness meaning, chip manufacturing edge roughness, what does ler mean
Line edge roughness, or LER, refers to the small, irregular waviness along the edges of a patterned feature on a chip — instead of a perfectly smooth, straight line, real…
semiconductor metrology explained, wafer inspection defect detection, CD-SEM overlay scatterometry, statistical process control fab, OCD critical dimension measurement
Metrology and inspection are how a fab knows whether the last 60 process steps actually worked, without waiting until the finished chip fails to find out. After nearly every…
non-recurring engineering cost, chip nre explained, semiconductor nre meaning, nre vs per-unit cost
Non-recurring engineering cost, or NRE cost, refers to the one-time upfront expense of designing and preparing a chip for manufacturing — covering things like design work…
opc lithography explained, optical proximity correction meaning, computational lithography opc, what does opc mean in chip manufacturing
Optical proximity correction, or OPC, is a computational technique that deliberately distorts the pattern on a photomask in precise, calculated ways so that after light…
photoresist explained, photoresist lithography meaning, positive vs negative photoresist, how does photoresist work
Photoresist is a light-sensitive chemical coating applied to a silicon wafer before lithography, one that chemically changes when exposed to light so that, after development, it…
plasma etching explained, RIE vs ICP etch, anisotropic etch semiconductor, dry etch process chip fabrication, plasma etch selectivity endpoint
Plasma etch is how a chip factory carves the pattern from a photomask into the actual silicon, layer by layer. After lithography exposes a resist pattern on the wafer, that…
poly gate etch explained, gate critical dimension control, polysilicon gate fabrication, gate etch stop on oxide, transistor gate patterning
Polysilicon etch is the process step that carves polycrystalline silicon into precise gate shapes, and for decades it was the single most critical etch step in the entire fab…
sti semiconductor explained, transistor isolation fab process, sti etch fill cmp, front end of line isolation, sti trench oxide fill
Shallow trench isolation (STI) is the structure that keeps neighboring transistors electrically separate, and it's one of the earliest steps in the front-end-of-line process that…
universal chiplet interconnect express, die to die interconnect standard, chiplet interoperability standard, ucie physical layer protocol layer, pcie cxl chiplet
UCIe (Universal Chiplet Interconnect Express) is the standardized protocol that lets chiplets from different vendors, built on different process nodes, actually talk to each other…
Wafer bonding is a process that joins two separately processed wafers face to face into a single mechanically and often electrically connected structure, enabling…
Wafer dicing is the process of physically cutting a finished, fully tested wafer apart into its individual chips, separating the many identical dies that were manufactured…
wafer probe test explained, dicing singulation semiconductor, chip packaging types, CoWoS advanced packaging, HBM TSV stacking, known good die
Once the last metal layer is done, a finished wafer is still just a fragile glass-thin disc holding hundreds of identical, untested chips. Everything up to this point…
Wafer thinning is a process that mechanically and chemically reduces a finished wafer's thickness, often down to a fraction of its original size, to enable thin chip packaging, 3D…
wire bonding explained, wire bonding vs flip chip, chip wire bonding meaning, what does wire bonding mean
Wire bonding is the traditional method of connecting a silicon die to its package by attaching extremely thin metal wires between connection pads on the die's edges…
semiconductor yield explained, wafer yield meaning, why yield matters, chip manufacturing yield
Yield is the percentage of chips on a wafer that come out good enough to sell, and it is the single number that decides more about a chip's real-world cost than almost anything…
metrology
White light interferometer (WLI) is an optical surface profiling instrument that uses broadband (white) light interference to measure 3D surface topography with sub-nanometer…
coherence scanning interferometry, csi, wli, phase shifting interferometry, optical surface profiler, mirau interferometer, 3d optical profilometry, metrology
White light interferometry is an optical surface profiling technique that uses broadband, low-coherence light to measure 3D surface topography, step heights, and areal surface…
design, esd protection network, power clamp, esd
Electrostatic Discharge (ESD) protection constitutes the dedicated on-chip network of high-current shunting devices engineered to safeguard sensitive gate dielectrics, thin tunnel…
300mm vs 200mm wafer, why are wafers 300mm, wafer size explained, why did wafers get bigger, 450mm wafer, dies per wafer
Modern fabs process silicon in the shape of 300-millimeter round wafers, not because that size is fundamentally special, but because it is the point where a bigger circle stopped…
why does a cpu need a heat sink, chip cooling explained, why do processors get hot, chip overheating
A chip needs cooling because every single transistor switching on and off wastes a small amount of energy as heat, and a modern processor switches billions of transistors billions…
why is silicon used for chips, why do chips use silicon, why is silicon used in semiconductors, silicon semiconductor material, why not another material for chips
Chips are made from silicon because silicon sits in a narrow, useful middle ground: pure silicon barely conducts electricity on its own, but adding tiny, precisely controlled…
bandgap, semiconductor, SiC, power, devices
Wide bandgap (WBG) power semiconductors, gallium nitride (GaN) High-Electron-Mobility Transistors (HEMT), and silicon carbide (4H-SiC) power MOSFETs constitute the foundational…
Active Learning for Wide-Bandgap Power Devices Active Learning for Wide-Bandgap Power Devices Introduction Active Learning for Wide-Bandgap Power Devices is an engineering…
Anomaly Detection for Wide-Bandgap Power Devices Anomaly Detection for Wide-Bandgap Power Devices Introduction Anomaly Detection for Wide-Bandgap Power Devices is an engineering…
Bayesian Parameter Estimation for Wide-Bandgap Power Devices Bayesian Parameter Estimation for Wide-Bandgap Power Devices Introduction Bayesian Parameter Estimation…
Causal Process Modeling for Wide-Bandgap Power Devices Causal Process Modeling for Wide-Bandgap Power Devices Introduction Causal Process Modeling for Wide-Bandgap Power Devices…
Chamber Matching for Wide-Bandgap Power Devices Chamber Matching for Wide-Bandgap Power Devices Introduction Chamber Matching for Wide-Bandgap Power Devices is an engineering…
Closed-Loop Yield Learning for Wide-Bandgap Power Devices Closed-Loop Yield Learning for Wide-Bandgap Power Devices Introduction Closed-Loop Yield Learning for Wide-Bandgap Power…