设备
shèbèi, 半导体设备, semiconductor equipment, 光刻机, ASML, 刻蚀设备, 制造设备
设备 — 半导体制造的"超级工具箱" 🔧🏭 拼音：shè bèi 一句话定义：半导体设备是将芯片设计图纸变为物理芯片的精密工业机器，是整个半导体产业链中技术门槛最高、附加值最大的环节之一——没有这些设备，再好的芯片设计都无法变为现实。 全球半导体设备市场规模约1200亿美元/年（2026年），是制造业皇冠上最耀眼的明珠之一。掌握关键设备，就掌握了芯片制造的命…
3,822 technical terms and definitions
shèbèi, 半导体设备, semiconductor equipment, 光刻机, ASML, 刻蚀设备, 制造设备
设备 — 半导体制造的"超级工具箱" 🔧🏭 拼音：shè bèi 一句话定义：半导体设备是将芯片设计图纸变为物理芯片的精密工业机器，是整个半导体产业链中技术门槛最高、附加值最大的环节之一——没有这些设备，再好的芯片设计都无法变为现实。 全球半导体设备市场规模约1200亿美元/年（2026年），是制造业皇冠上最耀眼的明珠之一。掌握关键设备，就掌握了芯片制造的命…
sti cmp planarization, trench fill oxide deposition, active area definition, isolation oxide densification
Shallow trench isolation (STI), high-aspect-ratio dielectric gap fill, chemical mechanical polishing (CMP), and channel mechanical stress engineering constitute the primary…
sti process flow, sti fill cvd, sti cmp planarization, isolation trench semiconductor
Shallow trench isolation (STI), high-aspect-ratio dielectric gap fill, chemical mechanical polishing (CMP), and channel mechanical stress engineering constitute the primary…
device isolation cmos, sti process fill, lcos isolation, isolation oxide semiconductor
Shallow trench isolation (STI), high-aspect-ratio dielectric gap fill, chemical mechanical polishing (CMP), and channel mechanical stress engineering constitute the primary…
sheet resistance map, sheet resistance uniformity mapping, wafer sheet resistance map, resistivity mapping four point probe
Four-point probe metrology measures sheet resistance by forcing current through two contacts and sensing voltage with two separate contacts, so the voltage channel carries almost…
voltage frequency pass fail map, speed binning, timing guardband, wafer probe test, semiconductor test engineering
A shmoo plot is a two-dimensional pass/fail map produced during chip testing — typically voltage on one axis and frequency (or timing margin) on the other — that shows exactly…
Shockley Transistor Corporation, Arnold Beckman, Beckman Instruments, four-layer diode, Shockley diode, Mountain View, Clevite
Shockley Semiconductor Laboratory was the company William Shockley founded in 1956 in Mountain View, California, with financial backing from Arnold Beckman's Beckman Instruments…
metrology
Spectroscopic ellipsometry and inline optical wafer metrology constitute the non-destructive physical measurement and defect detection disciplines that govern yield control across…
semiconductor etch, sic dry etching, sic plasma etching, sf6 o2, sic trench etch, etch mask sic
Read SiC dry etching through a plasma-physics and etch-rate/selectivity lens rather than a wet-chemistry lens. Silicon carbide's lattice is locked together by Si–C covalent bonds…
silicon carbide process, sic mosfet, sic wafer, wide bandgap fabrication
Wide bandgap (WBG) power semiconductors, gallium nitride (GaN) High-Electron-Mobility Transistors (HEMT), and silicon carbide (4H-SiC) power MOSFETs constitute the foundational…
sic diode switching, sic inverter efficiency, sic device aging, sic gate driver design
Silicon Carbide Power Module is a wide-bandgap semiconductor technology enabling superior high-temperature, high-frequency power switching through improved blocking voltage…
silicon carbide, wide bandgap, sic power
Wide bandgap (WBG) power semiconductors, gallium nitride (GaN) High-Electron-Mobility Transistors (HEMT), and silicon carbide (4H-SiC) power MOSFETs constitute the foundational…
sit, self aligned spacer patterning, spacer lithography, sit patterning, pitch halving
Sidewall Image Transfer (SIT) is the self-aligned patterning technique that uses the sidewall spacers deposited on a lithographically defined mandrel as the actual etch mask…
bipolar base collector emitter, heterojunction bipolar transistor fabrication, bicmos process integration, hbt speed cutoff frequency
A silicon-germanium heterojunction bipolar transistor is a vertical NPN device whose epitaxial base changes band structure and doping. Fabrication must grow a low-defect SiGe:C…
snr, metrology
SNR (Signal-to-Noise Ratio) is the ratio of the analytical signal to the noise level — where is the signal intensity and is the noise amplitude, quantifying the quality…
metrology
Spectroscopic ellipsometry and inline optical wafer metrology constitute the non-destructive physical measurement and defect detection disciplines that govern yield control across…
material science, silicon wafer, diamond cubic lattice, czochralski growth, native oxide, silicon dioxide, intrinsic silicon, electronic-grade silicon, band gap
Silicon is the element nearly every chip on Earth is built from — not because it's the best semiconductor on paper, but because it combines a workable band gap, an extraordinarily…
through silicon via TSV, micro bump pitch, copper to copper bonding, impedance controlled routing, chiplet signal integrity, 2.5D thermal management, thermal via hot spot, chiplet rework, passive substrate routing
A silicon interposer is a passive silicon substrate carrying embedded electrical interconnects that routes signals and power between multiple chiplets mounted on top of it…
photonics, chip, co-design, integration
Silicon Photonics Chip Co-Design is an integrated design methodology combining photonic optical components with electronic control circuits on a single silicon substrate — Silicon…
sic power, sic mosfet, wide bandgap semiconductor
Wide bandgap (WBG) power semiconductors, gallium nitride (GaN) High-Electron-Mobility Transistors (HEMT), and silicon carbide (4H-SiC) power MOSFETs constitute the foundational…
sic power device, sic substrate wafer, electric vehicle sic, sic inverter
Wide bandgap (WBG) power semiconductors, gallium nitride (GaN) High-Electron-Mobility Transistors (HEMT), and silicon carbide (4H-SiC) power MOSFETs constitute the foundational…
sic substrate manufacturing, sic crystal growth, sic wafer defect, sic epitaxy
Wide bandgap (WBG) power semiconductors, gallium nitride (GaN) High-Electron-Mobility Transistors (HEMT), and silicon carbide (4H-SiC) power MOSFETs constitute the foundational…
SiC boule growth, micropipe defect density, basal plane dislocation, wide bandgap power semiconductor, physical vapor transport growth, grind polish SiC hardness, power device reliability, automotive traction inverter, SiC substrate cost
Silicon carbide wafer manufacturing is the crystal growth and wafering process flow that produces wide-bandgap silicon carbide substrates for power semiconductor devices, and it's…
chip compilation, high-level synthesis ambition, automated layout, design abstraction, EDA history
A silicon compiler is a tool or approach that aims to translate a relatively high-level description of a desired chip function into the physical layout of an integrated circuit…
griffith fracture criterion 111 cleavage microcrack, back to back diode screening curve tracer bvcbo bvebo, stereomicroscope edge chipping quality gate ti 1954
Inspect the Bars: Dual Mechanical Crack Screening and Two-Junction Gate Slicing the ingot core into individual matchsticks in Step 23 yielded dozens of isolated silicon bars, but…
silicon latent heat of fusion 1787 kj kg density anomaly, silicon semiconductor to metallic melt transition rf coupling, floating solid silicon chunks optical pyrometer plateau 1414
Melt the Charge: Supplying 1414°C Latent Heat Through an RF Induction Susceptor Reaching silicon's 1414°C melting point on an optical pyrometer looks like a single milestone, but…
advanced packaging, cowos, 2.5d packaging, tsv interposer
Interposers are the substrates that carry 2.5D integration: a die-to-die wiring layer dense enough to route thousands of connections between chiplets that sit side by side.…
organic substrate bga, substrate trace routing, package substrate laminate, high density substrate
Advanced Packaging Interposer Substrate is a engineering infrastructure connecting semiconductor dies to external connections through elaborate multi-layer routing networks…
SiN film, PECVD nitride, LPCVD nitride, nitride applications
Silicon Nitride (SiN/Si3N4) Deposition encompasses the CVD processes — primarily LPCVD and PECVD — used to deposit silicon nitride films that serve as etch stops, hard masks…
fdsoi fully depleted, soi wafer fabrication, body biasing fdsoi, soi vs bulk cmos
Silicon-on-Insulator (SOI) substrate engineering, Fully Depleted SOI (FD-SOI) planar architectures, and dynamic back-gate body biasing constitute the engineered substrate…
substrate
Silicon-on-Insulator (SOI) substrate engineering, Fully Depleted SOI (FD-SOI) planar architectures, and dynamic back-gate body biasing constitute the engineered substrate…
crystal orientation, miller indices, 100, 110, 111, material science, wafer, crystallography
Silicon crystal orientations refer to the specific crystallographic planes used as the surface of silicon wafers — identified by Miller indices like (100), (110), and (111), each…
Active Learning for Silicon Photonics Active Learning for Silicon Photonics Introduction Active Learning for Silicon Photonics is an engineering workflow for integrated optical…
Anomaly Detection for Silicon Photonics Anomaly Detection for Silicon Photonics Introduction Anomaly Detection for Silicon Photonics is an engineering workflow for integrated…
Bayesian Parameter Estimation for Silicon Photonics Bayesian Parameter Estimation for Silicon Photonics Introduction Bayesian Parameter Estimation for Silicon Photonics is…
Causal Process Modeling for Silicon Photonics Causal Process Modeling for Silicon Photonics Introduction Causal Process Modeling for Silicon Photonics is an engineering workflow…
Chamber Matching for Silicon Photonics Chamber Matching for Silicon Photonics Introduction Chamber Matching for Silicon Photonics is an engineering workflow for integrated optical…
Closed-Loop Yield Learning for Silicon Photonics Closed-Loop Yield Learning for Silicon Photonics Introduction Closed-Loop Yield Learning for Silicon Photonics is an engineering…
Contamination Monitoring for Silicon Photonics Contamination Monitoring for Silicon Photonics Introduction Contamination Monitoring for Silicon Photonics is an engineering…
Cost and Cycle-Time Optimization for Silicon Photonics Cost and Cycle-Time Optimization for Silicon Photonics Introduction Cost and Cycle-Time Optimization for Silicon Photonics…
Critical Dimension Prediction for Silicon Photonics Critical Dimension Prediction for Silicon Photonics Introduction Critical Dimension Prediction for Silicon Photonics is…
Defect Excursion Detection for Silicon Photonics Defect Excursion Detection for Silicon Photonics Introduction Defect Excursion Detection for Silicon Photonics is an engineering…
Design of Experiments for Silicon Photonics Design of Experiments for Silicon Photonics Introduction Design of Experiments for Silicon Photonics is an engineering workflow…
Digital Twin Calibration for Silicon Photonics Digital Twin Calibration for Silicon Photonics Introduction Digital Twin Calibration for Silicon Photonics is an engineering…
Edge AI Deployment for Silicon Photonics Edge AI Deployment for Silicon Photonics Introduction Edge AI Deployment for Silicon Photonics is an engineering workflow for integrated…
Endpoint Detection for Silicon Photonics Endpoint Detection for Silicon Photonics Introduction Endpoint Detection for Silicon Photonics is an engineering workflow for integrated…
Equipment Health Monitoring for Silicon Photonics Equipment Health Monitoring for Silicon Photonics Introduction Equipment Health Monitoring for Silicon Photonics is…
Fault Detection and Classification for Silicon Photonics Fault Detection and Classification for Silicon Photonics Introduction Fault Detection and Classification for Silicon…
Federated Learning for Silicon Photonics Federated Learning for Silicon Photonics Introduction Federated Learning for Silicon Photonics is an engineering workflow for integrated…
Film Thickness Control for Silicon Photonics Film Thickness Control for Silicon Photonics Introduction Film Thickness Control for Silicon Photonics is an engineering workflow…