Site Flatness
metrology
Site Flatness is a wafer metrology parameter measuring the flatness (or thickness variation) within a small, localized area (site) on the wafer — typically measured as SFQR (Site…
435 technical terms and definitions
metrology
Site Flatness is a wafer metrology parameter measuring the flatness (or thickness variation) within a small, localized area (site) on the wafer — typically measured as SFQR (Site…
6 sigma, dpmo, defects per million, sigma level, process capability, semiconductor quality
Six Sigma (6σ) Yield is a quality standard that tolerates at most 3.4 defects per million opportunities (DPMO), corresponding to 99.99966% of outputs within specification…
small angle x-ray scattering, saxs, saxs metrology, transmission saxs, nanoscale morphology saxs
Small-angle X-ray scattering measures nanoscale electron-density variation by recording elastic X-rays deflected only slightly from a transmitted beam. The pattern can reveal…
soic, packaging
Small outline integrated circuit is the surface-mount package family with gull-wing leads on two sides that balances manufacturability, cost, and board density - it is widely used…
sop, packaging
Small outline package is the leaded surface-mount package family with gull-wing leads on two sides, widely used for memory and analog ICs - it offers mature manufacturability…
smart cut donor wafer blister formation prediction with machine learning, smart cut donor wafer blister formation prediction machine learning, smart cut, soi
Smart-Cut Donor Wafer Blister Formation Prediction with Machine Learning Introduction & Motivation Smart-Cut Donor Wafer Blister Formation Prediction with Machine Learning…
smo, source-mask optimization, lithography
Source-Mask Optimization (SMO) is a joint computational lithography technique that simultaneously co-optimizes the illumination source pupil shape and the photomask pattern…
what is a soc, system on chip explained, difference between chip and soc, what does soc mean, soc versus chip, system on a chip
Every SoC is a chip, but not every chip is a SoC, and the distinction is about what gets integrated onto one piece of silicon rather than how the silicon itself is manufactured.…
lithography
Soft Bake (Post-Apply Bake) Soft bake, often called post-apply bake (PAB), is the controlled thermal step after spin coating and edge treatment but before exposure. It removes…
fd soi, pdsoi, soi wafer, soi technology
Silicon-on-Insulator (SOI) substrate engineering, Fully Depleted SOI (FD-SOI) planar architectures, and dynamic back-gate body biasing constitute the engineered substrate…
advanced packaging
Advanced packaging is the set of technologies that connect, protect and cool silicon after it leaves the fab. It has moved from a cost-driven back-end afterthought to a primary…
packaging
Solder bump formation is the fabrication process that creates controlled solder volumes on die or wafer pads for subsequent flip-chip assembly - bump geometry quality drives joint…
packaging
Solder die attach is the die-attach technique using solder alloy to create metallurgical bond between die backside metallization and package substrate - it provides high thermal…
wafer sort, probe yield, cp yield, die yield, circuit probe, wafer test, production
Sort yield is the percentage of functional die identified during wafer-level electrical testing — measuring how many die pass probe testing before wafer dicing, providing an early…
sorter module wafer centering accuracy prediction machine learning, sorter module, wafer centering accuracy, sorter module wafer centering accuracy prediction
Sorter Module Wafer Centering Accuracy Prediction with Machine Learning Introduction & Motivation Sorter Module Wafer Centering Accuracy Prediction with Machine Learning addresses…
sorter wafer id read accuracy prediction machine learning, sorter wafer, id read accuracy, id ocr, sorter wafer id read accuracy prediction, sorter wafer id, wafer id read
Sorter Wafer ID Read Accuracy Prediction with Machine Learning Introduction & Motivation Sorter Wafer ID Read Accuracy Prediction with Machine Learning addresses a central problem…
silicide contact, contact resistivity semiconductor, metal semiconductor contact, wrap around contact
Self-aligned silicides and nanoscale contact metallization architectures represent the material and thermodynamic interfaces engineered to establish low-resistance ohmic…
sd contact resistance, contact resistivity reduction, metal semiconductor contact, silicide contact resistance
Self-aligned silicides and nanoscale contact metallization architectures represent the material and thermodynamic interfaces engineered to establish low-resistance ohmic…
sige epitaxy channel strain, raised source drain process, selective epitaxial deposition, in-situ doped epitaxy
Source/Drain Epitaxial Growth Process — Precision semiconductor crystal growth technology enabling strain engineering, junction profile optimization, and contact resistance…
sadp self-aligned double patterning, saqp self-aligned quadruple patterning, spacer patterning pitch splitting, sidewall spacer lithography, sadp, saqp
Self-aligned multiple patterning is the pitch multiplication technique where sub-lithographic circuit features are defined not by direct optical resolution but through…
spare parts first wafer yield risk prediction, spare parts first, parts first wafer, first wafer yield, wafer yield risk, yield risk prediction, spare parts, parts first
Spare Parts First Wafer Yield Risk Prediction with Machine Learning Introduction & Motivation Spare Parts First Wafer Yield Risk Prediction with Machine Learning addresses…
semiconductor spare parts, spare parts optimization, spare parts stocking levels, fab spare parts management
Spare parts inventory management strategically stocks replacement components near semiconductor fabrication tools to minimize mean-time-to-repair (MTTR) and fab downtime.…
spatial computing hardware, spatial architecture, cgra, wafer scale engine, dataflow processor
Spatial computing definition and engineering boundary. in hardware architecture places many operations and storage resources at distinct physical locations and configures data…
spatial kriging wafer metrology interpolation machine learning, spatial kriging, wafer metrology interpolation, spatial kriging for wafer metrology interpolation
Spatial Kriging for Wafer Metrology Interpolation with Machine Learning Introduction & Motivation Spatial Kriging for Wafer Metrology Interpolation with Machine Learning addresses…
metrology
Spatial signature is the characteristic pattern of failures on a wafer — the unique fingerprint of a process issue, equipment problem, or systematic defect that appears…
spatial wafer level yield model prediction with machine learning, spatial wafer level yield model prediction machine learning, spatial wafer, level yield model, yield model
Spatial Wafer-Level Yield Model Prediction with Machine Learning Introduction & Motivation Spatial Wafer-Level Yield Model Prediction with Machine Learning addresses a central…
thin film ellipsometer, refractive index dispersion n k, delta psi ellipsometry, cauchy lorentz oscillator model, sub angstrom optical film metrology
Spectroscopic ellipsometry measures how reflection changes the polarization of light across a wavelength range and uses that information to infer thin-film thickness, complex…
manufacturing equipment, optical metrology, thin film measurement, refractive index n k, dispersion model, surface roughness measurement
Spectroscopic ellipsometry measures how reflection changes the polarization of light across a wavelength range and uses that information to infer thin-film thickness, complex…
ellipsometry wafer mapping, ellipsometric thickness mapping, spectroscopic ellipsometry map, wafer optical constants mapping, imaging ellipsometry mapping, ellipsometry mapping metrology
Spectroscopic ellipsometry mapping converts polarization changes at registered positions into spatial models of film thickness, optical constants, roughness, composition, or other…
keyword spotting chip, neural engine voice, always on audio processor, wake word detection chip
Speech and Audio Processing Chip: Always-On Keyword Spotting Engine — ultra-low-power neural network for wake-word detection enabling voice assistant activation with <1 mW standby…
serial peripheral interface, sclk, mosi, miso, chip select, qspi, ospi, spi bus
SPI protocol is a synchronous serial interface in which a controller supplies clock and chip select while exchanging data over separate output and input lines. Its simple…
spiking neural network chip yield prediction, spiking neural network, neural network chip, network chip yield, chip yield prediction, spiking neural, neural network, chip yield
Spiking Neural Network Chip Yield Prediction with Machine Learning Introduction & Motivation Spiking Neural Network Chip Yield Prediction with Machine Learning addresses a central…
Spin Hall Effect, Rashba-Edelstein Kinetics, Spin Accumulation, and Harmonic Hall Metrology 1. Introduction: Spin-Orbit Coupling and Spintronics Spin-orbit coupling (SOC) is…
semiconductor spin qubit quantum dot silicon germanium exchange coupling J, singlet triplet S T0 qubit spin relaxation T1 dephasing T2 star
Semiconductor Spin Qubits: Exchange Coupling, Singlet-Triplet Dynamics, and Pauli Spin Blockade 1. Introduction: Spin Qubits in Silicon and Germanium Semiconductor spin…
metrology
Split-CV (Split Capacitance-Voltage) is the semiconductor metrology technique that quantifies interface state density (Dit) at the insulator-semiconductor interface by measuring…
sputter chamber shield redeposition prediction machine learning, sputter chamber, shield redeposition prediction, pvd, sputter chamber shield redeposition prediction
Sputter Chamber Shield Redeposition Prediction with Machine Learning Introduction & Motivation Sputter Chamber Shield Redeposition Prediction with Machine Learning addresses…
sputter deposition step coverage prediction machine learning, sputter deposition, step coverage prediction, pvd, sputter deposition step coverage prediction, deposition step
Sputter Deposition Step Coverage Prediction with Machine Learning Introduction & Motivation Sputter Deposition Step Coverage Prediction with Machine Learning addresses a central…
pvd sputtering, sputtering process, physical sputtering, sputter deposition, sputtered film, sputtering mechanism, sputtering pressure, sputtering gas scattering, sputtering angular distribution, sputtered atom energy, sputtering film stress
Sputtering converts ion energy at a solid target into a transported flux of atoms, clusters, reflected neutrals, electrons, photons, and sometimes ions that build a film on…
sraf, sub-resolution assist features, lithography
Sub-Resolution Assist Features (SRAFs) are tiny patterns placed on the photomask near main features that are too small to print on the wafer but improve the imaging quality of…
sram bitcell scaling, sram read write margin, 6t sram stability, sram vmin
SRAM Scaling and Yield is the canary-in-the-coalmine indicator for semiconductor process health — where the densest, most variation-sensitive circuit on the chip (the 6-transistor…
metrology
Stability in metrology is the consistency of measurement results obtained on the same part over an extended period of time — tracking whether a semiconductor metrology tool's…
metrology
Stability in metrology is the consistency of measurement results over time — a stable measurement system produces the same results today, next week, and next month when measuring…
3d transistor stacking, monolithic 3d integration, sequential transistor fabrication, tier bonding process
Stacked Transistor Integration is the advanced manufacturing approach that creates multiple active device layers in the vertical dimension through sequential fabrication or layer…
staining, defect, metrology
Staining (Defect Delineation) is a wet-chemical or electrochemical technique that creates optical contrast between semiconductor regions of different doping type, concentration…
packaging
Standoff height is the distance between the bottom of the package body and the PCB surface after mounting - it influences solder-joint shape, cleaning access, and thermomechanical…
noise margin design, glitch analysis, functional noise chip, noise propagation
Static Noise Analysis (SNA) is the technique for verifying that noise on internal chip signals does not cause functional failures — analyzing whether signal disturbances…
static sims metrology, static secondary ion mass spectrometry, surface static sims
Static SIMS (secondary ion mass spectrometry) is the low-dose regime of surface static SIMS analysis in which the primary ion beam is held far below the fluence that would…
statistical mechanics, statistical physics, thermodynamic ensembles, partition function, boltzmann distribution, quantum statistics, fermi dirac, bose einstein, semiconductor statistical mechanics
Statistical mechanics explains macroscopic matter by treating microscopic states probabilistically. Instead of following every atom, electron, phonon, spin, or defect, it defines…
stem, metrology
Spectroscopic ellipsometry and inline optical wafer metrology constitute the non-destructive physical measurement and defect detection disciplines that govern yield control across…
lithography
A Stepper is a lithography tool that projects a reticle (mask) pattern onto photoresist-coated wafers using a step-and-repeat process — exposing one die (or a small group of dies)…