1,686 technical terms and definitions
refresh controller DRAM, tREFI DRAM, tRFC refresh cycle time, per-bank refresh, REFpb, all-bank refresh, refresh overhead DRAM, DRAM temperature compensated refresh
DRAM Refresh Controller: Row-Scheduling Architecture, the Refresh-Tax Theory, and Per-Bank Refresh Application The refresh controller is the part of DRAM that never gets to rest.…
dram refresh cycle optimization prediction, dram refresh cycle, refresh cycle optimization, cycle optimization prediction, dram refresh, refresh cycle, cycle optimization
DRAM Refresh Cycle Optimization Prediction with Machine Learning Introduction & Motivation DRAM Refresh Cycle Optimization Prediction with Machine Learning addresses a central…
dram, dynamic random-access memory, 1T1C DRAM, DRAM cell architecture, DRAM refresh, DRAM storage capacitor, DRAM memory matrix, DRAM sensing, dram refresh fail bit count, fail bit count prediction
DRAM: Dynamic Random-Access Memory — Architecture, Retention Physics, and 1T1C Scaling Dynamic Random-Access Memory (DRAM) is the fundamental working memory of computing: it…
dram refresh interval drift prediction, dram refresh interval, refresh interval drift, interval drift prediction, dram refresh, refresh interval, interval drift, drift prediction
DRAM Refresh Interval Drift Prediction with Machine Learning Introduction & Motivation DRAM Refresh Interval Drift Prediction with Machine Learning addresses a central problem…
dram refresh overhead and capacity trade-offs, dram refresh overhead, refresh overhead capacity, overhead capacity trade-offs, dram refresh, refresh overhead, overhead capacity
DRAM Refresh Overhead and Capacity Trade-Offs Introduction & Motivation DRAM Refresh Overhead and Capacity Trade-Offs addresses a central problem in memory process control…
dram refresh rate optimization, dram refresh rate, refresh rate optimization, dram refresh, refresh rate, rate optimization
DRAM Refresh Rate Optimization with Machine Learning Introduction & Motivation DRAM Refresh Rate Optimization with Machine Learning addresses a central problem in DRAM refresh…
dram memory optimizing refresh rates in dram to balance power and data retention, dram memory optimizing, memory optimizing refresh, optimizing refresh rates, refresh rates dram, dram memory
DRAM Memory: Optimizing refresh rates in DRAM to balance power and data retention Introduction & Motivation DRAM Memory: Optimizing refresh rates in DRAM to balance power and data…
optimizing refresh rates in dram to balance power and data retention, optimizing refresh rates, refresh rates dram, rates dram to, dram to balance, to balance power, balance power data
Optimizing refresh rates in DRAM to balance power and data retention Introduction & Motivation Optimizing refresh rates in DRAM to balance power and data retention addresses…
dram refresh row hammer prediction, dram refresh row, refresh row hammer, row hammer prediction, dram refresh, refresh row, row hammer, hammer prediction
DRAM Refresh Row Hammer Prediction with Machine Learning Introduction & Motivation DRAM Refresh Row Hammer Prediction with Machine Learning addresses a central problem in DRAM…
next-generation dram technology, next-generation dram, dram technology
Next-Generation DRAM Technology Introduction & Motivation Next-Generation DRAM Technology addresses a central problem in memory process control and capacity-per-die prediction…
row hammer DRAM, rowhammer, aggressor row victim row, target row refresh, TRR DRAM, activation threshold DRAM, PRAC DDR5, refresh management RFM
DRAM Row Hammer: Disturbance Architecture, the Activation-Threshold Theory, and Target Row Refresh Application Row hammer is what happens when the same electrical margins this…
high bandwidth memory HBM, DRAM cell capacitor, DDR5 LPDDR5 memory, memory wall bandwidth
High-bandwidth memory (HBM) is DRAM stacked vertically and connected to its host through an interface thousands of bits wide, running beside the processor on an interposer rather…
sense amplifier DRAM, cross-coupled latch DRAM, folded bitline DRAM, bit line isolation transistor, DRAM bit line equalization, sense amp offset DRAM, Pelgrom law DRAM, regenerative sense amplifier
DRAM Sense Amplifier: Cross-Coupled Latch Architecture, Regenerative Feedback Theory, and the Folded-Bitline Application The sense amplifier is where a DRAM read actually becomes…
DRAM shallow trench isolation, shallow trench isolation DRAM, DRAM cell isolation, STI corner leakage, buried word line isolation, saddle fin transistor, DRAM active area isolation, STI gap fill DRAM, cell-to-cell leakage DRAM, STI aspect ratio scaling
DRAM STI: Shallow Trench Isolation Architecture, Corner-Leakage Theory, and the Cell-to-Cell Isolation Moat Shallow trench isolation (STI) is the etched, oxide-filled moat that…
dram storage capacitor aspect ratio prediction machine learning, dram storage, capacitor aspect ratio, dram sem, dram storage capacitor aspect ratio prediction
DRAM Storage Capacitor Aspect Ratio Prediction with Machine Learning Introduction & Motivation DRAM Storage Capacitor Aspect Ratio Prediction with Machine Learning addresses…
dram technology roadmap, dram technology, technology roadmap
DRAM Technology Roadmap Introduction & Motivation DRAM Technology Roadmap addresses a central problem in memory process control and capacity prediction: how to Predict capacity…
dram cell capacitor, dram high k capacitor, 4f2 dram cell, dram refresh reliability
High-bandwidth memory (HBM) is DRAM stacked vertically and connected to its host through an interface thousands of bits wide, running beside the processor on an interposer rather…
twin cell DRAM, differential sense amplifier DRAM, dummy cell reference DRAM, common-mode rejection DRAM, radiation hardened DRAM, twin cell sensing
DRAM Twin-Cell Reference: Differential Sensing Architecture, Common-Mode Cancellation Theory, and the Reliability-Density Trade-Off A twin-cell reference replaces the sense…
dram voltage and timing drift prediction, dram voltage timing, voltage timing drift, timing drift prediction, dram voltage, voltage timing, timing drift, drift prediction
DRAM Voltage and Timing Drift Prediction with Machine Learning Introduction & Motivation DRAM Voltage and Timing Drift Prediction with Machine Learning addresses a central problem…
dram word line resistance variation prediction, dram word line, word line resistance, line resistance variation, resistance variation prediction, dram word, word line
DRAM Word Line Resistance Variation Prediction with Machine Learning Introduction & Motivation DRAM Word Line Resistance Variation Prediction with Machine Learning addresses…
row address strobe column address strobe active low latch, t_rcd ras to cas delay sense amplifier settling time, ras cas timing cost traded against pin count savings
Tell the Chip Which Half of the Address It Is Looking At 1. Add the Signal the Multiplexing Scheme Was Missing Step 1 showed that the same 8 pins can carry a row address and then…
ras activates entire row simultaneously access transistors, row wide refresh side effect single cell access, ras only cycle deliberate row refresh tool mechanism
One Strobe Touches Every Cell in a Row, Whether You Asked It To or Not 1. Follow RAS Past Addressing Into What It Actually Does to the Array Step 2 treated as an addressing…
row column split r times c determines refresh count, wide rows fewer refresh cycles more sense amp load, refresh overhead t_rc tradeoff row count sense amplifier power
Choose the Array's Shape, and the Refresh Count Falls Out of That Choice 1. Turn Step 3's Row-Wide Refresh Into a Concrete Cycle Count Step 3 established that one -only cycle…
automated row stepping host triggers refresh generically, refresh overhead fraction r times t_rc over t_ret, responsibility moves to chip where retention physics lives
Let the Chip Remember Which Row Comes Next, So the System Does Not Have To 1. State What Manual Row-Stepping Would Demand of the Host System Step 4 established that a complete…
multiplexed addressing architecture outlives specific numbers, pin count constraint propagated never resolved away, first dram series about periphery not cell interior
Classify and Close: What Every Later DRAM Keeps, and What Was Only 64K's Own Arithmetic 1. Separate the Enduring Mechanism From This Generation's Particular Numbers Every step…
1t1c dram cell trench stacked capacitor transition, dram capacitor area shrinks faster than signal charge requirement, dram scaling 1974 geometry limit leaves the plane for the third dimension
Why a Shrinking Cell Forces the Capacitor Off the Plane: Planar Charge Storage Collapses Under Scaling 1. State the Constraint the 1968 Cell Never Had to Face The 1T1C cell fixes…
trench versus stacked capacitor dram 3d cell geometry, dram scaling substrate trench punchthrough vs stacked topography, 1t1c capacitor area perimeter height product third dimension
Step 2 — Choose Between Etching Down (Trench) and Building Up (Stacked): Two Geometries for the Third Dimension 1. The Fundamental Fork: Substrate Etching vs. Over-Gate…
deep reactive ion etch trench capacitor aspect ratio limits, dram trench sidewall capacitance scales with etch depth, aspect ratio dependent etching arde and void free fill dram
Step 3 — Build the Trench: Etch Depth as the New Area Budget 1. Sidewall Area Replaces Planar Pitch By cutting a high-aspect-ratio vertical cavity into the silicon substrate…
stacked capacitor crown cylinder hsg poly storage node dram, stacked dram alpha soft error immunity dielectric isolated, stacked capacitor topography step height depth of focus
Step 4 — Build the Stacked Capacitor: Rising Above the Transistor 1. Climbing Vertically into the Free Space Above the Gate Rather than excavating deep into the fragile silicon…
trench versus stacked quantitative aspect ratio comparison dram, why dram industry forked trench versus stacked capacitor camps, dram storage capacitance 35 femtofarad area budget comparison
Step 5 — Compare the Two Geometries on the Same Electrical Terms: Why the Industry Forked 1. Equalizing the Electrical Baseline: The 35 fF Target When trench and stacked…
trench dram buried plate oxide collar parasitic punchthrough, vertical parasitic mosfet suppression buried strap dram, trench to trench bulk punchthrough depletion merge isolation
Step 6 — Isolate the Trench Capacitor From the Substrate: Buried Plates and Oxide Collars 1. The Parasitic Perils of a Shared Silicon Bulk Because the trench capacitor is carved…
trench dram keyhole void pinch off knudsen diffusion limit, conformal lpcvd dielectric and polysilicon trench fill dram, step coverage aspect ratio dependent deposition dram yield
Step 7 — Fill the Trench Without Leaving a Void: Conformal Deposition and the Pinch-Off Limit 1. Knudsen Diffusion and the Threat of Premature Pinch-Off Once a high-aspect-ratio…
chemical mechanical polishing preston equation dram global planarity, stacked dram array periphery step height depth of focus loss, bpsg reflow vs oxide cmp planarization stacked capacitor dram
Step 8 — Planarize the Stacked Capacitor for the Layers Above It: Chemical Mechanical Polishing and Global Planarity 1. The Topographic Cliff Between Memory Array and Peripheral…
trench vs stacked cost accounting femtofarad per mask dram, dram process steps mask count cmp vs deep rie capital cost, storage capacitance yield figure of merit fab economics dram
Step 9 — Measure the Payoff: Capacitance Recovered Per Unit of Process Complexity 1. The Cost-Accounting of 3D Charge Storage Escaping the planar scaling crisis required adding…
dennard scaling breakdown 3d capacitor evolution dram, trench vs stacked legacy 3d semiconductor architecture dram, when planar physics failed 3d dimension solved moore law
Step 10 — The 1974 Retrospective: When Leaving the Plane Became the Only Way Forward 1. The Immutable Circuit Law and the Collapse of Two Dimensions Robert Dennard’s 1968 1T1C…
lvs, verification, design rule check, physical verification
Physical verification constitutes the essential electronic design automation signoff methodology that rigorously validates whether an integrated circuit layout satisfies foundry…
design rule check, design rules, physical verification drc
Physical verification constitutes the essential electronic design automation signoff methodology that rigorously validates whether an integrated circuit layout satisfies foundry…
drc, design rule check, design
Physical verification constitutes the essential electronic design automation signoff methodology that rigorously validates whether an integrated circuit layout satisfies foundry…
calibre physical verification, design rule violation, layout vs schematic check, parasitic extraction pex
Physical verification constitutes the essential electronic design automation signoff methodology that rigorously validates whether an integrated circuit layout satisfies foundry…
generative models
DreamBooth fine-tunes diffusion models to generate specific subjects or styles from few example images. Approach: Fine-tune entire model (or LoRA) on images of subject with unique…
generative models
DreamBooth is the fine-tuning approach that personalizes a diffusion model to a subject concept using instance images and class-preservation regularization - it can produce strong…
multimodal ai
DreamBooth is a personalization method that fine-tunes diffusion models to generate a specific subject from text prompts - It enables subject-consistent generation from a small…
reinforcement learning
Dreamer is a model-based reinforcement learning agent that achieves state-of-the-art sample efficiency by learning a world model from sensory inputs and training a policy entirely…
reinforcement learning advanced
Dreamer is a model-based reinforcement-learning family that trains policies from imagined latent trajectories - Dreamer learns latent dynamics and optimizes actor-critic…
Dreamer Latent Imagination RL Introduction & Motivation Dreamer Latent Imagination RL addresses a central problem in sequential decision making via deeprl: how to Learn a policy…
Dreamer Latent Imagination RL (Extended Study) Introduction & Motivation Dreamer Latent Imagination RL (Extended Study) addresses a central problem in sequential decision making…
Dreamer Latent Imagination RL (Extended Study) Introduction & Motivation Dreamer Latent Imagination RL (Extended Study) addresses a central problem in sequential decision making…
3d vision
DreamFusion is the text-to-3D optimization framework that distills 2D diffusion priors into a 3D representation through rendered views - it introduced score-distillation guidance…
multimodal ai
DreamFusion is a text-to-3D optimization method using 2D diffusion priors to supervise 3D scene generation - It creates 3D content without paired text-3D training data. What Is…
monitoring, shift
Drift Monitoring for data drift and model drift detects when input distributions or model performance change over time, triggering alerts for investigation and potential…