3,822 technical terms and definitions
production, random sampling, virtual wafer, defect placement simulation, process parameter variation, yield distribution, tail risk, design process interaction, stochastic yield model
Monte Carlo simulation for yield uses repeated random sampling to model the full statistical distribution of semiconductor yield, simulating thousands of virtual wafers each…
TSMC founder, foundry model pioneer, pure-play foundry, fabless enabler, semiconductor industry structure
Morris Chang is the founder of Taiwan Semiconductor Manufacturing Company, TSMC, and the person most associated with pioneering the pure-play foundry business model, in which…
metal-oxide-semiconductor field-effect transistor, Atalla and Kahng, gate oxide, silicon dioxide, CMOS, Frank Wanlass, Solid State Device Research Conference
The 1959 MOSFET was the first working metal-oxide-semiconductor field-effect transistor, made at Bell Labs by Mohamed Atalla and Dawon Kahng in November 1959, demonstrated at…
transistor scaling, Moore's law, device shrinking, scaling benefits, semiconductor scaling
MOSFET scaling is the practice of making the transistors on an integrated circuit progressively smaller from one technology generation to the next, which is the engine behind…
mosfet scaling 1970s step 19 push toward one micron node metrology, push toward one micron node metrology
MOSFET Scaling (1970s): Step 19 — Pushing Toward the 1-Micron Node, Metrology Limits Measurement control becomes as hard a problem as process control. As the integrated flow…
semiconductor company, DRAM leader, MK4096, address multiplexing, memory industry history, 1970s memory maker
Mostek was an American semiconductor company, active primarily in the 1970s and early 1980s, best known for its leadership in dynamic memory and for the MK4096, the 4-kilobit DRAM…
Texas Instruments spin-off, semiconductor startup, DRAM company origin, 1969 founding, memory maker
The founding of Mostek in 1969 is a notable episode in semiconductor history, as the company was started by engineers who left Texas Instruments to pursue memory and other…
mainboard, system board, ATX, chipset, CPU socket, UEFI, PCIe slot
A motherboard is the main printed circuit board of a computer, the platform that physically holds the processor, memory modules and expansion cards and supplies the electrical…
magnetic tunnel junction, mtj, stt mram, sot mram, embedded mram
Emerging memory is the umbrella term for a class of non-volatile memories — chiefly MRAM, ReRAM, and PCM — that store a bit not as trapped electric charge, the way DRAM and NAND…
mueller matrix spectroscopic ellipsometry, mueller ellipsometry, full mueller matrix polarimetry, depolarization ellipsometry, mueller matrix optical metrology, mueller matrix ellipsometer
Mueller matrix ellipsometry measures how a sample transforms a set of incident polarization states into output Stokes vectors over wavelength, angle, azimuth, or position. Its 4×4…
4x4 polarization matrix, diattenuation retardance depolarization, off diagonal asymmetry detection, cross polarized elements, advanced overlay metrology, structural asymmetry detection
Mueller matrix scatterometry is an advanced form of optical scatterometry that measures a sample's complete four-by-four Mueller matrix — all sixteen elements capturing…
lithography
Multi-beam e-beam lithography uses multiple parallel electron beams writing simultaneously to overcome the fundamental throughput limitation of conventional single-beam…
lithography, beamlet array, independent blanking, raster scan writing, IMS Nanofabrication, curvilinear mask, inverse lithography, EUV mask write time, KLA MBMW
A multi-beam mask writer patterns a mask using a massively parallel array of more than 250,000 individually-controllable electron beamlets firing simultaneously, finally breaking…
multi bridge channel structure, mbcfet vs nanosheet, mbcfet fabrication process, mbcfet electrostatics
Multi-Bridge Channel FET (MBCFET): Architecture, Physics & Process Integration The Multi-Bridge Channel Field-Effect Transistor (MBCFET) is Samsung Foundry's proprietary…
multi core processor, multicore processor, chip-multiprocessor, chip multiprocessor
A multi-core processor integrates more than one processor core in a computing component. Each core provides an execution engine capable of running an instruction stream. Caches…
mcmm signoff analysis, pvt corner timing, on chip variation ocv, statistical timing analysis
Static Timing Analysis and timing closure constitute the deterministic, vector-independent verification methodology engineered to exhaustively prove that every synchronous path…
chiplet integration, die to die interface, ucle, heterogeneous integration chip
Multi-Die Chiplet Design is the architectural approach of decomposing a monolithic chip into multiple smaller dies (chiplets) that are co-packaged and interconnected — enabling…
chiplet interconnect architecture, ucle chiplet standard, chiplet disaggregation, heterogeneous chiplet integration
Multi-Die Chiplet Design Methodology is the chip architecture approach that disaggregates a monolithic SoC into multiple smaller silicon dies (chiplets) connected through…
chiplet interconnect standard, ucIe chiplet, die to die interface, heterogeneous chiplet
Multi-Die Chiplet Integration is the advanced packaging architecture that decomposes a monolithic SoC into multiple smaller silicon dies (chiplets) interconnected through…
chiplet interconnect technology, chiplet packaging architecture, chiplet die to die interface, chiplet heterogeneous integration
Advanced packaging is the set of technologies that connect, protect and cool silicon after it leaves the fab. It has moved from a cost-driven back-end afterthought to a primary…
chiplet design methodology, multi die eda, die to die interface, heterogeneous integration design
Multi-Die and Chiplet Design Methodology is the EDA and architectural approach to designing systems composed of multiple smaller silicon dies (chiplets) connected through advanced…
reticle limited design, stitch boundary overlay, oversized die lithography field
Multi-Die Reticle Stitching A lithography scanner's exposure field has a hard maximum size — roughly 26mm by 33mm for standard DUV and EUV scanners — and a reticle can only…
chiplet integration methodology, die-to-die interconnect, heterogeneous integration methodology, multi-die partitioning strategy
Advanced packaging is the set of technologies that connect, protect and cool silicon after it leaves the fab. It has moved from a cost-driven back-end afterthought to a primary…
advanced packaging
Multi-Layer Transfer is the sequential process of transferring and stacking multiple thin crystalline device layers on top of each other — building true monolithic 3D integrated…
multi-modal microscopy, correlative microscopy, microscopy data fusion, semiconductor correlative microscopy, hypermodal microscopy
No single microscope sees a semiconductor defect in all the ways that matter. Secondary electrons reveal surface form, diffraction reveals crystal orientation, EDS or EELS reveals…
sadp, saqp, double patterning, self aligned multiple patterning, pitch multiplication, lithography
Self-aligned multiple patterning is the pitch multiplication technique where sub-lithographic circuit features are defined not by direct optical resolution but through…
lithography
Multi-Patterning Decomposition is a computational lithography process that mathematically assigns features of a single design layer to multiple sequential lithographic exposures…
sadp saqp, self aligned patterning, double patterning design, pitch walking, lithography
Self-aligned multiple patterning is the pitch multiplication technique where sub-lithographic circuit features are defined not by direct optical resolution but through…
sadp, saqp, self-aligned double patterning, self-aligned quadruple patterning, pitch division, spacer patterning, lithography
Self-aligned multiple patterning is the pitch multiplication technique where sub-lithographic circuit features are defined not by direct optical resolution but through…
self-aligned quadruple patterning, sadp saqp process flow, pitch splitting techniques, litho-etch-litho-etch process, sadp, saqp
Self-aligned multiple patterning is the pitch multiplication technique where sub-lithographic circuit features are defined not by direct optical resolution but through…
mpw, shuttle, shared wafer, multi project, mpw program
Yes, Multi-Project Wafer (MPW) is a core service enabling cost-effective prototyping by sharing wafer and mask costs — with MPW programs available for 180nm ( 10K per project)…
multi-project wafer, mpw, business
Multi-project wafer (MPW) is a cost-sharing service where multiple chip designs from different customers are placed on the same reticle, dramatically reducing prototyping…
MPW, shared reticle field, mask cost sharing, die allocation, standard PDK, advanced node access, startup prototyping, rapid tape out iteration, shared wafer dicing
Multi-project wafer service, universally abbreviated MPW, is a cost-sharing fabrication model where multiple chip designs from different, entirely unrelated customers get tiled…
metal layers, wiring layers, vias, interconnect delay, chip wiring
Multilevel interconnect is the use of multiple stacked layers of metal wiring, separated by insulating layers and joined by vertical connections, to wire together the enormous…
packaging
Multiple reflow survival is the ability of a semiconductor package to withstand repeated solder reflow exposures without structural or electrical degradation - it is important…
multiple-detect test patterns, N-detect fault coverage, multi-detect ATPG, fault detection diversity, structural test pattern generation, semiconductor test
N-Detect ATPG and Multiple-Detection Test Pattern Generation N-Detect ATPG and Multiple-Detection Test Pattern Generation Executive Overview N-detect automatic test pattern…
n-type silicon, donor-doped semiconductor, majority electrons, phosphorus-doped silicon, arsenic doping, antimony doping, NMOS
An n-type semiconductor is a semiconductor, most often silicon, that has been doped with donor atoms such as phosphorus, arsenic or antimony so that mobile electrons greatly…
high-na euv lithography, numerical aperture euv, 0.55 na euv, next generation euv
High-NA EUV is the next EUV scanner generation: it keeps the 13.5 nm wavelength but raises numerical aperture from 0.33 to 0.55, giving chipmakers sharper imaging for 2 nm-class…
charge-trap memory, ONO stack, macaroni channel, word line, channel-hole etch, multi-deck stacking, CMOS-Under-Array, Xtacking, wafer-to-wafer bonding, confront planar nand's cell-to-cell interference wall
Confront Planar NAND's Cell-to-Cell Interference Wall 1. 1. Confront Planar NANDs Cell to Cell Interference Wall Every NAND flash cell before the move to three dimensions stored…
charge-trap memory, ONO stack, macaroni channel, word line, channel-hole etch, multi-deck stacking, CMOS-Under-Array, Xtacking, wafer-to-wafer bonding, confront the tunnel-oxide atomic-scale limit
Confront the Tunnel-Oxide Atomic-Scale Limit 2. 2. Confront the Tunnel Oxide Atomic Scale Limit A second wall sat beside the first, and it was arguably harder to argue around…
charge-trap memory, ONO stack, macaroni channel, word line, channel-hole etch, multi-deck stacking, CMOS-Under-Array, Xtacking, wafer-to-wafer bonding, the industry's decision: stop shrinking, go vertical
The Industry's Decision: Stop Shrinking, Go Vertical 3. 3. The Industrys Decision Stop Shrinking Go Vertical Faced with cell-to-cell interference that grew worse every time…
charge-trap memory, ONO stack, macaroni channel, word line, channel-hole etch, multi-deck stacking, CMOS-Under-Array, Xtacking, wafer-to-wafer bonding, what going vertical actually changes about the cell
What Going Vertical Actually Changes About the Cell 4. 4. What Going Vertical Actually Changes About the Cell Turning the memory array on its side is not just a packaging trick…
charge-trap memory, ONO stack, macaroni channel, word line, channel-hole etch, multi-deck stacking, CMOS-Under-Array, Xtacking, wafer-to-wafer bonding, charge-trap storage replaces the floating gate
Charge-Trap Storage Replaces the Floating Gate 5. 5. Charge Trap Storage Replaces the Floating Gate The core memory mechanism in 3D NAND is charge-trap storage, not the floating…
charge-trap memory, ONO stack, macaroni channel, word line, channel-hole etch, multi-deck stacking, CMOS-Under-Array, Xtacking, wafer-to-wafer bonding, the ono film stack: oxide, nitride, oxide
The ONO Film Stack: Oxide, Nitride, Oxide 6. 6. The ONO Film Stack Oxide Nitride Oxide The charge-trap layer never sits by itself against the channel; it is sandwiched between two…
charge-trap memory, ONO stack, macaroni channel, word line, channel-hole etch, multi-deck stacking, CMOS-Under-Array, Xtacking, wafer-to-wafer bonding, the macaroni channel: a cylindrical transistor
The Macaroni Channel: a Cylindrical Transistor 7. 7. The Macaroni Channel a Cylindrical Transistor The silicon channel that carries current through a 3D NAND string is not a flat…
charge-trap memory, ONO stack, macaroni channel, word line, channel-hole etch, multi-deck stacking, CMOS-Under-Array, Xtacking, wafer-to-wafer bonding, one vertical string replaces many planar cells
One Vertical String Replaces Many Planar Cells 8. 8. One Vertical String Replaces Many Planar Cells Put the macaroni channel and the layer-by-layer word lines together and…
charge-trap memory, ONO stack, macaroni channel, word line, channel-hole etch, multi-deck stacking, CMOS-Under-Array, Xtacking, wafer-to-wafer bonding, word-line and control-gate layering
Word-Line and Control-Gate Layering 9. 9. Word Line and Control Gate Layering Each horizontal layer in a 3D NAND stack is built from an alternating pair of thin films: one film…
charge-trap memory, ONO stack, macaroni channel, word line, channel-hole etch, multi-deck stacking, CMOS-Under-Array, Xtacking, wafer-to-wafer bonding, manufacturing sequence: stack deposition
Manufacturing Sequence: Stack Deposition 10. 10. Manufacturing Sequence Stack Deposition Before a single channel hole is etched, a 3D NAND die begins as a flat stack…
charge-trap memory, ONO stack, macaroni channel, word line, channel-hole etch, multi-deck stacking, CMOS-Under-Array, Xtacking, wafer-to-wafer bonding, manufacturing sequence: channel-hole etch and charge-trap deposition
Manufacturing Sequence: Channel-Hole Etch and Charge-Trap Deposition 11. 11. Manufacturing Sequence Channel Hole Etch and Charge Trap Deposition Once the full alternating stack is…
charge-trap memory, ONO stack, macaroni channel, word line, channel-hole etch, multi-deck stacking, CMOS-Under-Array, Xtacking, wafer-to-wafer bonding, why etching more layers gets progressively harder
Why Etching More Layers Gets Progressively Harder 12. 12. Why Etching More Layers Gets Progressively Harder The channel-hole etch described in the previous step does not stay…